Senior Memory Mask Design Engineer

Job Title

Senior Memory Mask Design Engineer

Role Summary

Lead physical layout and mask design for high-performance digital memory subsystems at advanced CMOS process nodes. The role focuses on architecture and layout of bit-cell arrays, sense amps, I/O blocks, decoders and associated control logic, along with verification and tape-out readiness.

Work includes directing custom and compiler-driven layouts, resolving physical-design issues, and coordinating with cross-functional teams while mentoring junior engineers.

Experience Level

Senior — typically requires 6+ years of proven experience in memory layout for advanced CMOS processes.

Responsibilities

Primary responsibilities include hands-on layout leadership, verification ownership, and technical mentorship.

• Implement IC layout for high-speed CMOS memory circuits at advanced nodes (3nm, 5nm, 7nm and below).
• Lead architecture and layout design of memory subsystems: control logic, sense amplifiers, I/O blocks, bit-cell arrays and decoders.
• Direct custom layout and verification of complex memory cells and establish methodologies for compiler-driven flows.
• Own physical verification activities including DRC, LVS, density analysis and tape-out checks.
• Identify and resolve complex physical-design issues in compiler-generated layouts; mentor junior engineers on methodologies.
• Provide IR drop and electromigration (EM) mitigation guidance and establish robust layout methodologies.
• Drive development and optimization of memory compilers for performance, area and manufacturability.
• Coordinate with cross-functional teams and represent the memory-layout team in technical discussions.

Requirements

Must-have technical skills and experience; listed concisely. Educational degree requirements are summarized separately below.

• Proven experience with memory layout in advanced CMOS process nodes and high-performance memory types.
• Strong knowledge of industry-standard EDA tools (Cadence toolset) for layout and verification.
• Familiarity with layout fundamentals: various bitcell types, decoder design, matched devices, symmetrical layout, and signal shielding.
• Experience with floorplanning, block-level routing and macro-level assembly.
• Knowledge of top-level verification practices including EM/IR checks and layout-dependent effects (LOD, dummification, fills).
• Experience driving tape-out quality checks and resolving layout dependent manufacturing issues.
• Ability to lead technical efforts, mentor engineers, and influence multi-disciplinary project decisions.
• Nice-to-have: experience developing or optimizing memory compilers and prior ownership of compiler-driven memory flows.

Education Requirements

B.E. / B.Tech. or M.Tech. in Electronics (or equivalent degree) is specified in the source; the posting also allows equivalent practical experience. The original posting specifies 6+ years of proven experience in memory layout for advanced CMOS processes as the experience-equivalent guidance.

About the Company

Company: NVIDIA

Headquarters: Santa Clara, California, USA

NVIDIA is a global leader in accelerated computing, renowned for its innovative solutions in AI and digital twins that transform diverse industries. The company specializes in networking technologies, providing end-to-end InfiniBand and Ethernet solutions for servers and storage that optimize performance and scalability. NVIDIA serves sectors such as high-performance computing, enterprise data centers, and cloud computing, constantly reinventing its products and services to stay ahead in the market.