Senior Memory Layout Engineer, DPG LPDDR

Job Title

Senior Memory Layout Engineer, DPG LPDDR

Role Summary

The Senior Memory Layout Engineer will develop full‑custom memory layouts for LPDDR products, focusing on bitcell creation, pitch matching, and peripheral integration. The role is embedded in a memory design team delivering array and peripheral blocks for DRAM/LPDDR devices.

Work involves collaborative design, physical implementation, verification closure, and addressing reliability and performance tradeoffs in advanced memory products.

Experience Level

Senior — typically 6+ years of relevant experience in memory layout and full‑custom layout development.

Responsibilities

Primary responsibilities include layout implementation, integration, verification support, and delivery of memory blocks.

• Create and optimize bitcell layouts and perform pitch‑matching across array and peripheral regions.
• Develop row decoder (XDEC) and column decoder (YDEC) layouts and integrate with memory arrays.
• Implement peripheral blocks and ensure correct physical integration with array hierarchy and decode path.
• Perform DRC/LVS debug and closure; collaborate with verification teams to resolve layout issues.
• Apply device physics and matching strategies to optimize parasitics, EM/ESD, and reliability.
• Plan, execute, and deliver layout blocks with minimal supervision; manage schedule, quality, and power tradeoffs.
• Support layout automation, data‑driven optimization, and debug/correlation workflows (including AI/ML techniques where applicable).

Requirements

Must‑have technical skills and experience required to perform the role.

• 6+ years of proven experience in memory and full‑custom layout development.
• Proficiency with Cadence Virtuoso for custom layout implementation.
• Hands‑on experience with Calibre DRC/LVS and closure methodologies.
• Strong understanding of DRAM/LPDDR architecture, array organization, and peripheral integration.
• Device physics expertise: transistor matching strategies, well/substrate engineering, parasitic optimization, EM/ESD considerations.
• Ability to work independently, take ownership, and meet schedules while maintaining quality and power targets.
• Nice to have: experience applying AI/ML to layout automation, optimization, or debug workflows.

Education Requirements

B.Tech / B.E. in Electronics, Electronics & Communications, or VLSI Engineering. M.Tech in Electronics Engineering, Microelectronics, or VLSI Engineering is listed as additional education. (No alternate "equivalent experience" phrasing specified.)

About the Company

Company: Micron Technology

Headquarters: Boise, Idaho, USA

Micron Technology is a global leader in memory and storage solutions, dedicated to transforming how the world uses information. The company offers a diverse portfolio of high-performance DRAM, NAND, and NOR memory products under the Micron and Crucial brands. With a commitment to customer focus and technological innovation, Micron drives advancements in artificial intelligence, 5G, and other data-centric applications, empowering users to learn, communicate, and progress.