Senior Manager - Systems Validation

Job Title

Senior Manager - Systems Validation

Role Summary

Lead a technical validation team responsible for FPGA silicon bring-up, validation, debug, and sign-off. Coordinate cross-functional execution across design, firmware, applications, systems and global engineering teams to deliver validated FPGA products.

Define validation strategy, drive lab-based debug, and ensure technical closure of issues before product sign-off.

Experience Level

Senior-level — requires 13+ years of relevant industry experience and proven management of silicon validation teams.

Responsibilities

Primary responsibilities include planning and executing silicon validation, mentoring staff, and coordinating cross-functional closures.

• Lead FPGA silicon validation using established design flows, methodologies, and lab debug practices.
• Manage and mentor a technical validation team across multiple projects; assign ownership and track milestone delivery.
• Define validation strategies, execution plans, test coverage goals, and sign-off criteria for blocks and subsystems.
• Develop RTL-based and embedded C test designs for feature validation, bring-up, and system-level debug.
• Review specifications, validation plans, board schematics, and test requirements to ensure readiness.
• Conduct board bring-up and debug of complex silicon functions using oscilloscopes, logic analyzers, protocol exercisers/analyzers, and integrated logic analyzers.
• Perform root-cause analysis for design, silicon, board, firmware, and system-level issues; validate workarounds and fixes.
• File, track, and close issues in Bugzilla/Jira; provide status updates and risk assessments to stakeholders.
• Collaborate with global teams for deep-dive debug, technical reviews, and sign-off alignment.
• Document validation results and secure formal sign-off for completed validation activities.

Requirements

Must-have technical and leadership qualifications.

• Proven experience managing or leading silicon validation teams, including planning, execution tracking, and technical mentoring.
• Hands-on experience in FPGA silicon validation, board bring-up, lab debug, validation closure, and issue triage.
• Strong understanding of SERDES architecture, PMA features, equalization settings, eye capture, and validation of data rates up to 100G.
• Hands-on validation experience with one or more high-speed protocols (examples: JESD204B/C, PCIe Gen4/Gen5, USB 3.2, 1588 PTP, MIPI, MACsec).
• Familiarity with embedded processors and peripherals (SPI, I3C, UART, NoC, Trace, USB) and C programming for embedded test applications.
• Experience debugging digital logic and analog behavior on PCBs using oscilloscopes, digital analyzers, protocol exercisers/analyzers, and integrated logic analyzers (e.g., Synopsys Identify, Xilinx ChipScope, Altera SignalTap, Lattice Reveal).
• Ability to handle complex block- and subsystem-level test planning, failure isolation, workaround validation, and closure.
• Excellent written and verbal communication skills and the ability to present technical status and risks to engineering leadership.
• Strong commitment to quality, customer satisfaction, disciplined execution, and continuous improvement.

Education Requirements

BE/BTech or ME/MTech in Electronics, Electrical Engineering, Computer Engineering, or a related discipline. The posting specifies 13+ years of relevant industry experience.

About the Company

Company: Microchip

Headquarters: Chandler, Arizona, USA

Microchip is a leading semiconductor company focused on developing innovative solutions to enhance the human experience. With a commitment to empowering innovation, Microchip prioritizes the value of its employees by fostering a culture that supports their growth and contributions.