Senior Manager — SoC DFT Engineering

Job Title

Senior Manager — SoC DFT Engineering

Role Summary

Lead DFT architecture, implementation, integration, and verification for complex SoCs and subsystems, working directly with customer design teams within the Systems Solutions Group.

This is a hands-on, customer-facing senior engineering leadership role responsible for defining test strategies, driving post-silicon debug, mentoring DFT engineers, and delivering DFT solutions that enable tapeout and production success.

Experience Level

Senior-level. Requires 10+ years of hands-on SoC DFT experience (architecture through tapeout and production).

Responsibilities

Primary responsibilities include technical leadership of DFT activities across projects and close collaboration with cross-functional teams to ensure testability and production readiness.

• Lead DFT architecture, implementation, integration, and verification from specification through tapeout for complex SoCs and subsystems.
• Define and execute test strategies across scan/ATPG, memory BIST, logic BIST, and analog/PHY test insertion to meet coverage, yield, and cost targets.
• Develop and document DFT methodologies and guidelines using Synopsys EDA tools for customer projects.
• Drive post-silicon support: debug failures with test/validation teams and refine test patterns and production programs.
• Provide technical leadership and mentor DFT engineers through complex integration and design tradeoffs.
• Collaborate with RTL design, verification, physical design, and timing teams to ensure testability from architecture through signoff.
• Manage DFT project deliverables, timelines, and quality for customer engagements within the Systems Solutions Group.

Requirements

Must-have technical skills and proven experience for successful performance in this role. Nice-to-have items are indicated.

• Must-have: 10+ years hands-on SoC DFT experience with expertise in scan/ATPG, memory BIST, logic BIST, and analog test.
• Must-have: Proven track record leading DFT implementation on complex SoCs that have taped out and reached production.
• Must-have: Deep understanding of the full SoC design flow: microarchitecture, RTL, verification, timing analysis, and physical implementation.
• Must-have: Experience collaborating with design, verification, and physical implementation teams to resolve testability issues and influence architecture decisions.
• Must-have: Strong post-silicon debug skills and experience working with test engineering teams to improve production test programs.
• Must-have: Demonstrated technical leadership and mentoring ability; able to lead design reviews and advocate testable solutions.
• Nice-to-have: Experience with Synopsys DFT tools such as TetraMAX, DFT Compiler, or BIST Architect.

Education Requirements

Bachelor's or Master's degree in Electronics Engineering, Electrical Engineering, or a related field.

About the Company

Company: Synopsys

Headquarters: Mountain View, California, USA

Synopsys is a leading company in electronic design automation (EDA) and semiconductor IP solutions. It provides tools and services for designing and verifying complex semiconductor devices and systems. The company plays a pivotal role in the semiconductor industry, helping engineers innovate and deliver higher-quality products faster. Synopsys is committed to advancing technology standards and offers a range of software and hardware solutions to its clients globally.