Senior Manager, Silicon Design Engineering

Job Title

Senior Manager, Silicon Design Engineering

Role Summary

Lead timing-closure methodology and static timing analysis (STA) efforts for complex SoC and IP designs, including chiplet and 3D-stack interfaces. Serve as the STA and clocking technical lead, define timing targets, and ensure designs meet performance and power requirements.

Work cross-functionally with IP, domain, CAD, methodology and post-silicon teams to identify technical risks, scope feature changes, and drive delivery of high-quality silicon on schedule.

Experience Level

Senior — requires technical leadership experience. Typical experience: 4+ years with a relevant Master’s degree, or 6+ years with a relevant Bachelor’s degree (see Education Requirements for details).

Responsibilities

Primary responsibilities include technical leadership of timing closure and clocking across complex SoC designs and supervising execution teams.

• Define and establish timing closure methodologies and strategies for SoC and IP blocks.
• Oversee STA closure for complex SoC designs, including chiplet and 3D stack interfaces.
• Act as overall STA and global clocking lead; own architectural timing analysis and scoping of feature changes.
• Partner with design teams on clocking, floorplan, area, timing targets and performance sign-offs.
• Collaborate with IP, CAD, methodology, and domain teams to resolve technical challenges and risks.
• Support post-silicon debugging and resolution of timing issues.
• Manage silicon design projects and lead engineering teams.

Requirements

Must-have technical skills and experience (minimum years described in Experience Level):

• Experience using CAD and back-end EDA tools across the chip design flow (synthesis, simulation, equivalence checking, place-and-route, STA).
• Experience overseeing physical design of deep-submicron digital ASICs, including floorplanning, placement, CTS, routing, and timing closure.
• Proven experience owning global clock tree construction and analysis to optimize PPA.
• Practical STA closure experience to ensure timing at target speeds.
• Scripting experience (TCL, Perl, or Python) to automate design and signoff flows.
• Experience managing silicon design projects and leading engineering teams through delivery.
• Ability to understand SoC-level integration and trade-offs across performance and power.

Nice-to-have: Not specified.

Education Requirements

Master's degree (or foreign equivalent) in Electronics Engineering, Computer Science, Computer Engineering, Electrical Engineering, or a related field is required. Employer will accept a Bachelor's degree (or foreign equivalent) in those fields plus six (6) years of relevant experience as an alternative. Equivalent practical experience that matches the stated education/experience combinations is acknowledged.

About the Company

Company: Advanced Micro Devices

Headquarters: Sunnyvale, California, USA

Advanced Micro Devices, or AMD, is a global semiconductor company that designs and manufactures microprocessors, graphics processors, and related technologies for a variety of computing devices. Known for pushing the boundaries of innovation, AMD's mission is to deliver high-performance computing solutions for AI, data centers, gaming, and embedded applications. They foster a collaborative, inclusive culture focused on creativity and problem-solving, aiming to drive progress and excellence in technology.