Senior Manager, Design Verification Engineering

Job Title

Senior Manager, Design Verification Engineering

Role Summary

Lead a design verification team responsible for pre-silicon verification of complex SoCs and subsystems. Own verification strategy, architecture, methodology and delivery to signoff across products and business units.

Collaborate with architecture, design, emulation/FPGA, firmware and software teams; mentor engineers and drive verification innovation and quality improvements.

Experience Level

Senior - typically requires 12+ years of experience in digital pre-silicon verification and leadership across IP, subsystem, or SoC-level DV.

Responsibilities

Primary responsibilities include planning and delivering verification for complex SoCs and subsystems.

• Lead end-to-end SoC verification from planning to signoff and ensure functional and code coverage closure.
• Design and implement scalable UVM-based testbenches, DV flows, and verification methodologies.
• Verify microprocessor-based designs, AI/ML accelerators, NoC/interconnects, and high-speed peripherals.
• Collaborate with architecture, design, emulation, FPGA, firmware, and software teams to align verification and pre-silicon readiness.
• Develop and execute system-level use cases and perform performance verification across real-world scenarios.
• Apply formal verification techniques and define formal flows for IP and subsystem validation.
• Drive verification strategy leveraging formal, emulation, portable stimulus, and virtual platforms.
• Mentor and lead team members; plan tasks, track progress, and provide technical leadership.

Requirements

Must-have technical skills and experience:

• Hands-on expertise in Verilog/SystemVerilog and UVM-based testbench development and debugging.
• Proven record of verification closure using functional and code coverage at block, subsystem and SoC levels.
• Experience with NoC, bus and interconnect verification, and coverage analysis/optimization.
• Power-aware verification experience (UPF) including power analysis and optimization.
• Formal verification experience: flow definition, connectivity and property checking.
• Protocol verification experience for I2C, SPI, Ethernet, UART, AXI/AHB, DMA, and SVI3.
• Familiarity with gate-level simulations with timing annotation (GLS).
• Test planning, constrained-random verification, assertions, and transaction-level modeling.
• Understanding of processor-based systems (ARM, RISC-V, Tensilica), AI/ML accelerators; proficiency in C/C++, SystemC, and scripting (Python, TCL, Shell).
• Experience defining and implementing scalable DV flows and leading verification teams across global organizations.

Nice-to-have:

• Exposure to mixed-signal/analog verification (ADC/DAC/PLL/PHY).
• Experience with security and functional safety verification.
• Prior contributions to patents or publications.

Education Requirements

B.Tech or M.Tech (engineering) as specified by the employer.

About the Company

Company: Analog Devices

Headquarters: Norwood, Massachusetts, USA

Analog Devices is a leading global semiconductor company that bridges the physical and digital worlds, enabling breakthroughs at the Intelligent Edge. With a focus on innovation, ADI develops solutions that drive advancements in digitized factories, mobility, and digital healthcare. The company employs around 24,000 people globally and reported revenues exceeding $9 billion in FY24, creating technologies that transform lives across various sectors.