Senior Manager, Design Verification Applications Engineering

Job Title

Senior Manager, Design Verification Applications Engineering

Role Summary

Lead a regional applications engineering team that supports Synopsys design verification products (VCS, Verdi, VC Formal) for customer SoC projects in Taiwan and across Asia. The role balances hands-on technical leadership, customer escalations, and people management to ensure successful tape-outs.

Work closely with sales, R&D, and global field teams to drive customer adoption of verification methodologies, deliver technical training, and translate field feedback into product and process improvements.

Experience Level

Senior — requires substantial verification experience (typically 8+ years) with at least 3 years of people management or technical leadership experience.

Responsibilities

Own team delivery, customer engagements, and technical escalations for verification applications engineering across multiple accounts.

• Lead and manage a team of applications engineers supporting verification toolchains across customer accounts in Taiwan and Asia.
• Drive customer adoption of constrained-random verification, coverage closure, UVM techniques, and related methodologies.
• Provide technical guidance on complex SoC verification problems and decide when to deploy resources or escalate to R&D.
• Hire, mentor, and develop engineers to run customer engagements independently and grow into technical leaders.
• Coordinate with sales, R&D, and global field teams on account strategy, product feedback, and roadmap alignment.
• Oversee technical workshops, training sessions, and onsite customer support to accelerate verification schedules.
• Manage team workload and priorities across simultaneous customer projects to meet business objectives.

Requirements

Must-have technical and leadership competencies required to perform the role.

• 8+ years of hands-on design verification experience with deep expertise in SystemVerilog, UVM, constrained-random verification, and coverage-driven methodologies.
• Proven experience building, debugging, and optimizing testbenches and verification environments on production SoC projects.
• 3+ years of people management or technical leadership, including hiring, mentoring, and performance management.
• Practical experience deploying Synopsys verification tools (VCS, Verdi, VC Formal) in customer environments.
• Ability to manage customer escalations, prioritize resources, and make timely decisions under project pressure.
• Strong English communication skills, able to present technical content to engineers and executives.
• Willingness to travel locally within Taiwan and regionally across Asia for customer engagements and team development.
• Nice-to-have: extensive tape-out experience, prior customer-facing application engineering or field support roles, and experience influencing product roadmaps via customer feedback.

Education Requirements

Bachelor's or Master's degree in Electrical Engineering, Computer Science, or a related technical field, or equivalent hands-on verification engineering experience.

About the Company

Company: Synopsys

Headquarters: Mountain View, California, USA

Synopsys is a leading company in electronic design automation (EDA) and semiconductor IP solutions. It provides tools and services for designing and verifying complex semiconductor devices and systems. The company plays a pivotal role in the semiconductor industry, helping engineers innovate and deliver higher-quality products faster. Synopsys is committed to advancing technology standards and offers a range of software and hardware solutions to its clients globally.