Senior Manager / Deputy Director, ASIC Digital Design & IP Engineering

Job Title

Senior Manager / Deputy Director, ASIC Digital Design & IP Engineering

Role Summary

Lead a processor and SoC IP engineering organization responsible for architecture implementation, RTL development, integration, verification support, and silicon delivery. The role partners with architecture, verification, physical design, DFT, firmware, software, and program management to meet quality, schedule, power, performance, and area (PPA) targets.

Experience Level

Senior — minimum 12+ years of experience in digital IC/SoC/processor design and engineering leadership.

Responsibilities

The role combines technical ownership, program execution, and people management to deliver processor IP and SoC projects to tapeout.

• Lead end-to-end development of processor cores and subsystems from specification through tapeout.
• Define microarchitecture and drive RTL implementation for high-performance and low-power designs.
• Review RTL quality, synthesis results, timing-closure strategies, and integration readiness.
• Ensure compliance with functional, performance, power, reliability, and security requirements.
• Perform architectural tradeoff analysis and drive PPA optimization activities.
• Create project plans, allocate resources, track milestones, identify risks, and execute mitigation plans.
• Coordinate design reviews, signoff readiness, cross-functional alignment, and interactions with external partners.
• Build, mentor, and manage a high-performing processor design team; own hiring, performance discussions, and career development.
• Support Environmental, Health, Safety & Security requirements in engineering activities.

Requirements

Key must-have technical and leadership qualifications for the role.

• Minimum 12+ years of experience in digital IC/SoC/processor design with proven silicon delivery.
• Deep expertise in microarchitecture development.
• Hands-on experience with RTL design using Verilog/SystemVerilog.
• Strong knowledge of processor pipelines and memory subsystems.
• Experience with SoC integration and ASIC design flow.
• Proficiency in synthesis and timing analysis for PPA closure.
• Experience leading medium to large engineering teams.
• Strong communication, leadership, and stakeholder management skills.

Nice-to-have:

• Experience with RISC-V, MIPS, ARM, ARC, or custom processor architectures.
• Experience with advanced process nodes (7nm, 5nm, 3nm and beyond).
• Expertise in multicore processors, AI accelerators, or high-performance computing architectures.
• Experience leading geographically distributed teams and complex cross-site programs.

Education Requirements

Required: Bachelor's or Master's degree in Electronics Engineering, Computer Engineering, Electrical Engineering, Computer Science, or a related technical field. Preferred: Master's degree or PhD.

About the Company

Company: GlobalFoundries

Headquarters: Saratoga Springs, New York, USA

GlobalFoundries is a leading contract manufacturer for the global semiconductor industry, with facilities in multiple countries, including the USA. The company develops a broad portfolio of semiconductor technologies and employs around 13,000 people worldwide. GlobalFoundries focuses on enhancing competitiveness in specialized application solutions and fostering innovation in mobile communications, consumer electronics, and automotive applications.