Senior Manager, ASIC Digital Design

Job Title

Senior Manager, ASIC Digital Design

Role Summary

Lead a high-speed PHY digital design team responsible for IP architecture, microarchitecture and delivery for PHY IPs (working on advanced nodes such as 12nm and below). The role oversees the full digital design lifecycle from specification through silicon and SoC integration, and partners with analog, verification, and physical-design teams.

Manage and mentor a distributed team, drive technical direction and process improvements, and deliver high-quality, production-ready IPs on schedule.

Experience Level

Senior — 12+ years of relevant ASIC digital design experience.

Responsibilities

Core responsibilities include technical leadership, delivery management, and cross-functional collaboration:

• Lead and mentor a team of digital designers focused on high-speed PHY IPs.
• Own IP release schedules and ensure quality of deliverables.
• Define digital architecture and microarchitecture for PHY IPs and sub-functions.
• Manage the full digital design flow from specification to silicon and SoC integration.
• Drive problem solving, silicon bring-up, debug and continuous improvement activities.
• Collaborate closely with analog, verification, and physical-design teams to ensure reliable mixed-signal interfaces.
• Coordinate with domain specialists across geographies on core technical initiatives.
• Plan and manage team tasks, timelines and technical priorities.

Requirements

Must-have technical skills and experience; separate list of desirable skills follows.

• Proven ownership of digital design for at least one PHY IP family: ONFI, DDR, LPDDR, MIPI or PCIe — from specification through silicon.
• Strong RTL development skills (Verilog) and proficiency with scripting for design and automation.
• Experience with timing closure, DFT, synthesis, lint and CDC methodologies.
• Knowledge of asynchronous domain transfer schemes and standard control interfaces (APB, JTAG).
• Familiarity with RTL-to-GDS flows and silicon bring-up/debug processes.
• Experience working with analog teams on mixed-signal data paths.
• Effective written and verbal communication skills and ability to work in cross-functional, globally dispersed teams.
• Demonstrated team leadership and task planning/management experience.

Nice-to-have:

• Experience leading R&D or future-technology development projects.
• Prior experience on advanced process nodes (12nm and below).

Education Requirements

M.S./MTech or B.S./B.E. in Electronics (listed). No other degree or certification language was provided.

About the Company

Company: Micron Technology

Headquarters: Boise, Idaho, USA

Micron Technology is a global leader in memory and storage solutions, dedicated to transforming how the world uses information. The company offers a diverse portfolio of high-performance DRAM, NAND, and NOR memory products under the Micron and Crucial brands. With a commitment to customer focus and technological innovation, Micron drives advancements in artificial intelligence, 5G, and other data-centric applications, empowering users to learn, communicate, and progress.