Senior Logic Design Engineer

Job Title

Senior Logic Design Engineer

Role Summary

Join the UnifabriX VLSI team to design next-generation rack-level architectures that increase application performance and reduce cost. Lead implementation and delivery of ASIC IP/modules from specification through silicon and FPGA prototyping.

Experience Level

Senior — 8+ years of hands-on ASIC development experience.

Responsibilities

Primary responsibilities include:

• Architect, implement, and verify RTL for ASIC projects using Verilog.
• Drive IP/module development from requirements to synthesis, place-and-route, and timing closure.
• Develop and manage synthesis/P&R constraints and perform timing analysis to meet performance targets.
• Design and integrate CPU subsystems and high-speed interfaces (PCIe, DDR, HBM, NVMe, Ethernet).
• Support FPGA prototyping and lab bring-up for validation and debug.
• Automate flows and verification tasks using Python and scripting.
• Collaborate with cross-functional teams and mentor junior engineers.

Requirements

Must-have:

• 8+ years of hands-on ASIC development experience.
• Strong RTL coding skills in Verilog.
• Experience with design flow activities: synthesis, place-and-route, timing constraints and closure.
• Experience with digital CPU subsystems and high-speed interfaces (PCIe, DDR, HBM, NVMe, Ethernet).
• Proficiency in Python or similar scripting for automation and verification.
• Proven ability to learn new technical domains and lead IP/module projects.
• Effective team player with good communication skills.

Nice-to-have:

• Experience with FPGA development and Altera/Xilinx build flows.
• Hands-on FPGA lab debug experience (e.g., ChipScope, SignalTap).

Education Requirements

Bachelor's degree in Electrical Engineering, Software Engineering, or Computer Science.

About the Company

Company: UnifabriX

Headquarters: Haifa, Israel

Stealth-mode startup developing scalable hardware and software technologies to accelerate, virtualize and transform datacenters into secure workload-centric infrastructures. Focus areas include VLSI and rack-level architectures; backed by venture capital and industry leaders.