Senior Leader, Electrical & Optical Systems Engineer

Job Title

Senior Leader, Electrical & Optical Systems Engineer

Role Summary

Member of Qualcomm Central Hardware Systems (CHS) delivering next-generation electrical and optical interconnect technologies for AI, hyperscale datacenter, networking, and HPC systems. The role defines end-to-end architecture, drives system/product development, and leads cross-disciplinary teams spanning silicon, photonics, packaging, PCB, and rack-scale infrastructure.

Experience Level

Senior. Preferred: 15+ years of relevant experience. Minimum: typically 8–10+ years of system/package design or technology engineering experience depending on academic credential.

Responsibilities

Lead technical strategy and execution for electrical-optical interconnect systems from concept to productization.

• Define end-to-end architecture for interconnect solutions using 112G/224G and emerging 448G SerDes, CPO/NPO, CPC/NPC, and flyover architectures.
• Lead system design and performance closure across SerDes/PHY, EIC/PIC integration, transceiver subsystems, packaging, PCB channels, connectors, cables, optics, power delivery, thermal, and mechanical design.
• Own SI/PI methodology and end-to-end link analysis (channel budgeting, COM, jitter, crosstalk, insertion/return loss) and simulation-to-silicon correlation.
• Drive electrical-optical DSP architecture and algorithms including TX/RX equalization, CDR, adaptive filtering, FEC, and impairment compensation.
• Develop system-level models and trade-off studies across bandwidth, reach, power, latency, reliability, manufacturability, cost, and scalability.
• Provide technical leadership and coordinate roadmaps across silicon, package, optics, platform, and software organizations; mentor senior technical staff.

Requirements

Must-have technical skills and experience required for immediate contribution; preferred items listed after.

• Must-have: Demonstrated success productizing 112G and/or 224G PAM4 electrical or optical communication systems.
• Must-have: Deep expertise in high-speed SerDes architectures, PAM4 communications, electrical-optical DSP algorithms, SI and PI, and EIC/PIC co-design and heterogeneous integration.
• Must-have: Hands-on experience with simulation and analysis tools such as ADS, HFSS, CST, HSPICE, MATLAB, Python, Cadence Sigrity, Lumerical, Zemax, Verilog-A/SystemVerilog, COM analysis tools, and IBIS-AMI modeling.
• Must-have: Proven ability to drive system-level performance closure across package, PCB, connector, cable, optics and platform domains.
• Nice-to-have: Experience productizing 224G+ and emerging 448G solutions, co-packaged / near-packaged optics (CPO/NPO), CPC/NPC, flyover optical/copper, silicon photonics, chiplets and UCIe.
• Nice-to-have: Familiarity with Ethernet, PCIe, NVLink, OIF CEI, IEEE 802.3, and other interconnect standards; record of influencing standards and technology roadmaps.

Education Requirements

Minimum qualifications specify a Bachelor's, Master’s, or PhD in Chemical Engineering, Electrical Engineering, Mechanical Engineering, or a related field with corresponding years of experience: Bachelor's +10 years, Master's +9 years, or PhD +8 years of system/package design or technology engineering experience. Preferred fields include Electrical Engineering, Optical Engineering, and Physics. Equivalent practical experience may be acceptable as specified in the minimum qualifications.

About the Company

Company: Qualcomm

Headquarters: San Diego, California, United States

Qualcomm is a global leader in semiconductor and telecommunications equipment, specializing in mobile technologies and innovations. Known for its Adreno GPUs, the company provides solutions enabling advancements in mobile gaming, AI, VR/AR, and autonomous driving. Qualcomm's cutting-edge technology and commitment to high-performance, power-efficient designs drive the evolution of mobile graphics and connectivity worldwide.