Senior Lead STA Engineer

Job Title

Senior Lead STA Engineer

Role Summary

Work as a senior ASIC/STA engineer on physical implementation and static timing analysis for high-performance, low-power SoC/IP development. Collaborate with architects, RTL designers, place-and-route teams and verification to achieve timing closure and meet power/performance/area targets.

Experience Level

Senior level. Preferred: 5+ years of STA-focused experience; note minimum qualifications vary by degree (see Education Requirements).

Responsibilities

The role focuses on STA, timing closure, ECO development and PPA optimization across process corners.

• Perform static timing analysis and identify critical timing bottlenecks.
• Develop and apply timing constraints and signoff flows across corners and modes.
• Prepare and implement complex ECOs (timing and physical) for timing convergence.
• Use industry tools (Tempus, PrimeTime, Genus, Innovus, ICC, or equivalent) in physical implementation flows.
• Optimize designs for performance, power and area and apply power-minimization techniques.
• Automate analysis and flows using scripting (Perl, TCL) and CAD/STA automation methods.
• Collaborate with cross‑functional teams to drive timing closure and product integration.

Requirements

Core technical skills and experience required for day‑to‑day execution.

• Proven experience in static timing analysis and timing closure on complex designs.
• Hands-on with STA and physical implementation tools such as PrimeTime/Tempus, Genus, Innovus, ICC, or equivalents.
• Strong experience preparing and applying complex ECOs for timing convergence across multiple corners.
• Demonstrated ability to diagnose and fix extreme critical timing paths and implement timing fixes.
• Proficiency in automation and scripting (Perl and TCL).
• Strong fundamentals in digital implementation and PPA optimization.
• Excellent debugging, problem solving, and cross-team communication skills.

Nice-to-have:

• Experience with deep submicron process technology nodes.
• Knowledge of high-performance and low-power implementation methods.
• Familiarity with Tweaker and physical PT ECO toolchains.

Education Requirements

Bachelor's degree in Science, Engineering, or a related field plus 3+ years of ASIC design/verification/validation/integration experience; OR Master's degree in Science, Engineering, or a related field plus 2+ years of relevant experience; OR PhD in Science, Engineering, or a related field plus 1+ year of relevant experience. (These degree-and-years combinations are the posted minimum qualifications.)

About the Company

Company: Qualcomm

Headquarters: San Diego, California, United States

Qualcomm is a global leader in semiconductor and telecommunications equipment, specializing in mobile technologies and innovations. Known for its Adreno GPUs, the company provides solutions enabling advancements in mobile gaming, AI, VR/AR, and autonomous driving. Qualcomm's cutting-edge technology and commitment to high-performance, power-efficient designs drive the evolution of mobile graphics and connectivity worldwide.