Senior Lead Physical Design Engineer
QualcommJob Title
Senior Lead Physical Design Engineer
Role Summary
Work on physical design (PD) of ASIC/SoC blocks from netlist through GDSII, owning floorplanning, P&R, timing closure and signoff activities. Collaborate with RTL, timing, power, and verification teams and contribute to methodology and flow improvements.
Experience Level
Senior-level. Typical candidates have 4–10 years of physical design experience; minimum hardware engineering experience expectations depend on degree (see Education Requirements).
Responsibilities
Primary responsibilities focus on end-to-end physical design delivery and cross-team coordination.
- Execute full PD ownership from netlist to GDSII, including floorplanning, P&R, and signoff readiness.
- Implement and validate low-power techniques (Voltage Islands, power domains) and PDN strategies.
- Debug and resolve congestion, clock-tree synthesis (CTS), and timing closure issues.
- Perform and verify sign-off flows (PV/PDN/STA/FV/CLP/Scan-DRC) and collaborate with sign-off teams.
- Develop and maintain scripts and automation to improve flows (TCL, Perl, Python).
- Drive methodology improvements and implement best practices across global teams.
- Communicate status, risks, and issues to stakeholders and coordinate cross-functional fixes.
Requirements
Critical technical skills and practical PD experience required for successful execution of the role.
- Thorough knowledge of ASIC place-and-route methodology and flows.
- Hands-on experience with full PD flow including HM-level PV, LEC, low-power checks, PDN work, and STA closure.
- Strong experience debugging congestion and CTS problems.
- Expertise with place-and-route tools such as Cadence Innovus or Synopsys Fusion Compiler.
- Familiarity with sign-off methodologies and tools (power, timing, functional verification, constraint/lint checks, scan/DRC).
- Proficiency in scripting for automation (TCL, Perl, Python).
- Proven ability to work effectively in global, cross-functional teams and to communicate technical status clearly.
- Practical physical design experience in the 4–10 year range is typical for this role.
Nice-to-have:
- Experience with advanced low-power flows and sign-off at advanced nodes.
- Previous ownership of complex SoC block delivery and cross-block integration.
Education Requirements
Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or a related field with 3+ years of hardware engineering experience; OR Master's degree in those fields with 2+ years' experience; OR PhD in those fields with 1+ year of experience. Equivalent practical experience is accepted.
About the Company
Company: Qualcomm
Headquarters: San Diego, California, United States
Qualcomm is a global leader in semiconductor and telecommunications equipment, specializing in mobile technologies and innovations. Known for its Adreno GPUs, the company provides solutions enabling advancements in mobile gaming, AI, VR/AR, and autonomous driving. Qualcomm's cutting-edge technology and commitment to high-performance, power-efficient designs drive the evolution of mobile graphics and connectivity worldwide.
