Senior / Lead Design Verification Engineer (Formal & Simulation)

Job Title

Senior / Lead Design Verification Engineer (Formal & Simulation)

Role Summary

Lead verification strategy and execution for complex, high-performance SoC blocks using a combination of formal verification and constrained-random UVM simulation. Work with RTL designers and architects to drive designs to sign-off and eliminate deep-cycle architectural bugs.

Experience Level

Senior-level. Requires 8+ years of ASIC/SoC design verification experience.

Responsibilities

Deliver verification sign-off for high-risk blocks and subsystems by selecting and executing the appropriate mix of formal and simulation techniques.

• Develop verification strategies and detailed testplans partitioning features between formal and constrained-random simulation.
• Architect and implement block-level and end-to-end formal environments; write SystemVerilog Assertions (SVA), assumptions, and helper models.
• Build and scale UVM-based simulation environments: sequences, monitors, scoreboards, and constrained-random tests.
• Debug and root-cause complex RTL bugs not easily exposed by simulation alone.
• Define hybrid sign-off criteria and merge simulation and formal metrics to achieve coverage closure.
• Collaborate with designers and architects to clarify specifications and resolve issues.

Requirements

Core technical skills and experience required for the role.

• Experience: 8+ years in ASIC/SoC design verification with tape-out experience.
• Formal verification: Expert in property/model checking, sequential equivalence, and SVA; experience using formal-friendly constraints and state-space reduction techniques (abstraction, induction, black-boxing, cut-points).
• Simulation & UVM: Advanced SystemVerilog and UVM architecture experience; strong OOP design patterns for verification.
• Tools: Experience with formal tools (Cadence JasperGold, Synopsys VC Formal, OneSpin) and simulators/debuggers (Synopsys VCS, Cadence Xcelium, Verdi).
• Protocols & domain: Experience verifying high-performance protocols (AXI, CHI, PCIe, CXL or similar) and deep understanding of CDC/RDC, arbiters, pipelines, caches, and credit-based flow control.
• Automation: Strong scripting skills (Python, Perl, or Tcl) to automate regressions and parse multi-tool results.
• Soft skills: Strong analytical "break-the-design" mindset, clear communicator, able to lead technical initiatives independently.

Education Requirements

Bachelor's or Master's degree in Electrical/Electronic Engineering, VLSI, Embedded Systems or closely related field (ECE/EEE/VLSI/Embedded Systems).

About the Company

Company: SiFive

Headquarters: San Mateo, California, United States

SiFive is a pioneering company in the RISC-V ecosystem, focused on transforming the future of computing by delivering high-performance, data-intensive RISC-V solutions. Their compute platforms empower leading technology firms to innovate across various markets, including AI, machine learning, and automotive sectors. SiFive is recognized for its commitment to ongoing innovation and fostering collaboration among talented teams, impacting lives by enabling advanced chip design.