Senior Layout Engineer - DPG Layout

Job Title

Senior Layout Engineer - DPG Layout

Role Summary

Senior layout engineer responsible for developing and owning physical implementation of critical analog, mixed-signal, and custom digital blocks at block and partition/full-chip level. The role leads layout automation and AI-enabled flows, ensures verification closure, and coordinates with design, CAD, verification, reliability, and program teams.

Experience Level

Senior - typically 6+ years of relevant analog/custom layout experience (posting specifies 6+ years).

Responsibilities

Deliver high-quality, manufacturable layouts and drive automation and verification to meet schedule and quality targets.

• Own development and physical implementation of critical analog, mixed-signal, and custom digital blocks; block-level and full-chip layout ownership.
• Lead layout implementation using AI-assisted and automated workflows, including copilot-based assistants and agentic AI flows to accelerate placement, routing, and optimization.
• Perform and automate physical verification (DRC, LVS, Antenna, ESD, EM/IR, TOTEM) and quality checks; drive verification closure.
• Drive on-time delivery of block and partition-level layouts with risk prediction and mitigation plans.
• Develop and deploy AI-enabled and scriptable methodologies for floorplanning, parasitic estimation, layout consistency checks, and best-practice enforcement.
• Identify manual bottlenecks and convert repetitive tasks into scalable automated flows (SKILL, Python, TCL, or agent-based flows).
• Provide technical leadership in planning, area and cycle-time estimation, delegation and execution.
• Collaborate with Design, CAD, Verification, Reliability, and Program Management to communicate technical risks, schedule impacts and optimization opportunities.
• Mentor engineers in analog layout fundamentals, automation-first approaches, design-for-quality and design-for-yield practices.

Requirements

Key qualifications and technical skills required and preferred for the role.

• Must-have: 6+ years of analog/custom layout design experience in advanced CMOS technology nodes.
• Must-have: Strong expertise in Cadence Virtuoso (VLE/VXL) and physical verification with Calibre DRC/LVS and hands-on verification closure.
• Must-have: Proven experience laying out critical analog blocks (examples: temperature sensors, PLLs, ADCs, DACs, LDOs, bandgaps, reference generators, charge pumps).
• Must-have: Hands-on experience with memory layouts (DRAM, SRAM, CAM, OTP) and array-to-periphery integration.
• Must-have: Deep understanding of analog layout fundamentals: matching/symmetry, EM, latch-up, coupling, crosstalk, IR-drop, shielding and guard-ring strategies, parasitics.
• Must-have: Strong ability to interpret design intent and constraints and produce manufacturable layouts.
• Must-have: Demonstrated experience defining, developing, and scaling AI-driven automation and AI-assisted methodologies for complex layout workflows.
• Must-have: Proven problem-solving skills in physical verification, debug, and layout optimization focused on yield improvement.
• Preferred: Experience developing scriptable automation (SKILL, Python, TCL) and integrating agent-based or copilot-assisted flows into production CAD environments.

Education Requirements

B.Tech in Electronics, Electronics & Communication, or VLSI Engineering; M.Tech in VLSI Design, Microelectronics, or Electronics Engineering.

About the Company

Company: Micron Technology

Headquarters: Boise, Idaho, USA

Micron Technology is a global leader in memory and storage solutions, dedicated to transforming how the world uses information. The company offers a diverse portfolio of high-performance DRAM, NAND, and NOR memory products under the Micron and Crucial brands. With a commitment to customer focus and technological innovation, Micron drives advancements in artificial intelligence, 5G, and other data-centric applications, empowering users to learn, communicate, and progress.