Senior Layout Engineer

Job Title

Senior Layout Engineer

Role Summary

Own transistor- and block-level full-custom layout for mixed-signal, SRAM, and custom-digital IP that supports Synthara's compute-in-memory SRAM. Work with custom-design, digital, and PD/STA teams to produce production-grade layouts meeting PPA, yield, and reliability targets.

Plan floorplans, implement device-level layouts with matching/guarding, and close DRC/LVS/PEX on advanced nodes while adapting analog techniques to FinFET/FDSOI and multi-patterning/EUV constraints.

Experience Level

Senior — 5+ years of custom layout experience (analog, SRAM, custom-digital).

Responsibilities

Primary tasks and collaborations expected from this role:

• Plan and implement full-custom layouts for standard cells, custom datapaths, and SRAM periphery/arrays.
• Develop floorplans and device-level layouts with production-grade matching, guarding, and isolation.
• Close DRC, LVS, and PEX on advanced process nodes (sub-28 nm, down to 4 nm and below).
• Coordinate with schematic owners; define pins/abstracts, LEF views, keep-outs, and macro tiling.
• Integrate with MBIST/scan wrappers, test hooks, and macro delivery processes.
• Collaborate with PD/STA and digital teams on timing, IR/EM, and post-layout extraction results.
• Automate repetitive layout tasks and maintain templates, checklists, and documentation (TCL, Python).
• Deliver tape-in and silicon-quality macros with correlated post-silicon parasitic reports and lessons learned.

Requirements

Must-have technical skills and experience; nice-to-have items listed separately.

• 5+ years in custom layout for analog, SRAM, and custom-digital IP with ownership from floorplan to sign-off.
• Practical experience on sub-28 nm nodes with FinFET/FDSOI process knowledge, multi-patterning/EUV constraints, and coloring.
• Strong analog layout techniques: common-centroid, interdigitation, matched routing, shielding/guard rings, substrate isolation.
• Ability to read extraction, timing, and PEX reports and iterate with designers and PD/STA; awareness of timing, IR, and EM impacts.
• Clear communication, rigorous documentation, and collaborative approach across custom design, digital, and backend teams.
• Nice-to-have: SRAM array/periphery experience, redundancy/repair, MBIST/scan routing, TCL/Python automation, DFM/DFY exposure, ESD/latch-up practices, LEF generation and macro floorplanning.

Education Requirements

Not specified.

About the Company

Company: Synthara

Headquarters: Zürich, Switzerland

Synthara develops ComputeRAM® hardware and software for efficient on-device AI, providing compilers, drivers, SDKs and tooling to enable AI workloads from microcontrollers to accelerators, with a focus on hardware/software co-design and developer usability.