Senior IP Verification Engineer (IOMMU-N)
SiFiveJob Title
Senior IP Verification Engineer (IOMMU-N)
Role Summary
Responsible for functional verification of IOMMU IP, owning verification planning, testbench development, stimulus generation, debugging, and coverage closure. The role works within the IP verification team to validate RTL against architectural specifications and integrate third-party VIPs.
This position requires the ability to perform deep root-cause analysis and to collaborate with design and integration teams. The role requires background checks and proof of right to work in India.
Experience Level
Senior — posting specifies 3+ years of design verification experience (preferably CPU verification).
Responsibilities
Lead and execute verification activities for IOMMU IP from planning through coverage closure.
- Analyze architecture and create verification plans with test cases, checkers, and coverage goals.
- Design and implement scalable, reusable SystemVerilog/UVM testbenches and environments.
- Develop constrained-random stimulus, complex sequences, and corner-case tests.
- Perform RTL and testbench debug using waveform tools (e.g., Verdi, SimVision) and root-cause analysis.
- Define, implement, and track functional and code coverage; write covergroups/coverpoints.
- Integrate and validate third-party VIPs and bus interfaces within the verification environment.
- Verify protocols and bus interfaces such as AXI, AHB, and PCIe.
- Write scripts and small tools to automate flows and data collection (Python/Perl).
Requirements
Must-have technical skills and experience; concise list of expectations.
- 3+ years in design verification (posting preference for CPU verification).
- Proficiency in SystemVerilog and UVM methodology.
- Strong object-oriented programming skills and experience with C/C++ where applicable.
- Experience writing tests and test plans for CPU-related features (x86, ARM, or RISC-V).
- Scripting experience, preferably Python; familiarity with Perl is a plus.
- Bus/interface knowledge such as AXI and PCIe; experience with bus VIPs.
- Experience integrating third-party VIPs into verification environments.
- CPU micro-architecture understanding sufficient to develop targeted tests and debug failures.
Education Requirements
Bachelor's or Master’s degree in Engineering (as stated in the posting).
About the Company
Company: SiFive
Headquarters: San Mateo, California, United States
SiFive is a pioneering company in the RISC-V ecosystem, focused on transforming the future of computing by delivering high-performance, data-intensive RISC-V solutions. Their compute platforms empower leading technology firms to innovate across various markets, including AI, machine learning, and automotive sectors. SiFive is recognized for its commitment to ongoing innovation and fostering collaboration among talented teams, impacting lives by enabling advanced chip design.
