Senior IP Verification Engineer

Role Summary

The Senior IP Verification Engineer role involves planning, developing, and executing the verification of new and existing features for AMD’s ASIC and FPGA System on Chips (SoCs). The primary goal is to ensure that there are no bugs in the final design, contributing to top-notch next-generation computing products.

Experience Level

Ideal candidates should have a substantial background in the industry, with at least 7 years of relevant experience for those with a Bachelor’s degree, or 5 years for those possessing a Master’s degree, specifically in Computer Engineering or Electrical Engineering.

Responsibilities

• Participate as a key member of a geographically distributed verification team to validate next-generation ASIC and FPGA products.
• Develop and execute test plans, implement testbenches, and create comprehensive test cases to ensure functional coverage closure.
• Conduct regression testing and contribute to the enhancement of verification infrastructure.
• Design directed and random verification tests based on project requirements.
• Investigate test failures, identify root causes, and collaborate with RTL and firmware engineers to resolve any design defects or test issues.
• Assess functional and code coverage metrics, and adapt tests as necessary to meet coverage requirements.
• Work closely with design, software, and architecture teams throughout the verification process.

Requirements

Applicants must be proficient in IP-level FPGA and ASIC verification and have knowledge of PCIe, CXL, or other I/O protocols. Proficiency in Verilog/SystemVerilog, alongside scripting skills in Perl or Python, is required. Candidates should have hands-on experience with SystemVerilog and UVM, with a solid understanding of the design flow and verification methodologies.

Education Requirements

A Bachelor’s degree in Computer Engineering or Electrical Engineering with at least 7 years of related experience, or a Master’s degree with 5 years of experience is required.