Senior Implementation Engineer

Job Title

Senior Implementation Engineer

Role Summary

Lead full-chip and hierarchical SoC physical design activities for advanced-node ASICs, driving chip closure from netlist to GDSII. Work within the physical implementation team and coordinate across RTL, synthesis, STA, package and backend teams to deliver tape-outs.

This role emphasizes technical leadership, problem solving on advanced nodes, and mentoring of junior engineers.

Experience Level

Senior-level. The posting requests 12+ years of hands-on ASIC physical design experience.

Responsibilities

Primary responsibilities include chip-level planning, integration, verification and sign-off.

• Lead chip-level hierarchical floorplanning and block-level integration.
• Drive partitioning strategy and partition push-down for hierarchical designs.
• Plan and own pin planning, IO planning, bump planning and bump routing.
• Define and execute power planning (ring/mesh/grid architectures, multi-voltage domain handling).
• Perform and manage full-chip CTS and clock architecture optimization.
• Execute and sign off physical verification (DRC, LVS, ERC, antenna checks) and ESD planning/implementation.
• Address full-chip closure issues: congestion, IR/EM, timing and SI/Noise analysis.
• Collaborate with RTL, synthesis, STA, package and backend teams to resolve integration issues and support tape-out.
• Mentor junior engineers and provide technical guidance on chip-level challenges.

Requirements

Must-have technical skills and preferred additions.

• Must-have: Demonstrated experience in chip-level hierarchical floorplanning, partitioning/partition push-down, pin/IO planning, bump planning and routing, and full-chip integration.
• Must-have: Experience with physical verification sign-off (DRC, LVS, ERC, antenna), IR drop analysis, SI/noise signoff and full-chip CTS.
• Must-have: Power planning experience for multi-voltage domains and UPF-aware flows.
• Must-have: Hands-on experience with leading EDA tools (examples: Cadence Innovus/ICC2, Synopsys Fusion Compiler, Tempus, PrimeTime, Mentor/Calibre for physical verification).
• Must-have: Experience in advanced process nodes (5nm/3nm/2nm or equivalent preferred).
• Nice-to-have: Track record of leading full-chip tape-outs and addressing last-mile tape-out issues.
• Nice-to-have: Knowledge of packaging interactions and bump/IO co-design.
• Nice-to-have: Ability to script and automate flows using Python, TCL or SKILL; familiarity with Cadence/Synopsys/Mentor ecosystems.

Education Requirements

Bachelor's or Master's degree in Electrical Engineering, Electronics, Microelectronics or a related field.

About the Company

Company: Arm

Headquarters: Cambridge, United Kingdom

ARM is a global leader in semiconductor and software design, driving innovation in computing technology. The company specializes in designing processors and systems that provide the essential building blocks for electronic devices. ARM's architecture is widely used in smartphones, servers, and IoT devices, and its collaborative culture fosters bold thinking, diversity, and high-impact benefits for its talented workforce.