Senior High-Speed Analog/RF System Architect

Job Title

Senior High-Speed Analog/RF System Architect

Role Summary

Lead the analog, RF, and high-speed SerDes architecture for CMOS SoCs that interface with graphene photonic interconnects. Define electrical architecture at the electronics–photonics boundary to meet system-level performance targets across bandwidth, power, reach, cost, and manufacturability.

Work cross-functionally with photonics, package/SI, analog and digital teams, and customers to translate deployment requirements into scalable SoC architectures.

Experience Level

Senior-level. Typical background: Ph.D. +5 years relevant experience or Master’s +8 years, or equivalent demonstrated impact in high-speed analog/RF and SerDes system architecture.

Responsibilities

Primary responsibilities focus on system architecture, link budget closure, roadmap ownership, and cross-domain collaboration.

• Own analog/RF and high-speed SerDes architecture for optical transceiver SoCs (drivers, TIAs, equalizers, ADC/DACs, PLLs, CDRs) targeting 112G/224G+ PAM4 and next-generation interconnects.
• Define and maintain Analog Product Requirement Specifications (PRS), verification plans, and PPA (performance, power, area) estimates.
• Drive system-level link budget closure across the complete electrical-to-optical channel, accounting for impairments, loss, reflection, crosstalk, and receiver noise.
• Own the Analog IP roadmap and align architecture direction with technology capabilities, EDA flows, and external design partners.
• Partner with photonics circuit designers, package electrical/SI architects, and SoC teams to reconcile architecture with PIC layout and packaging constraints.
• Prepare Customer Requirement Documents (CRDs) and engage directly with customers to ensure architectures meet deployment needs.
• Lead SoC concept and feasibility studies, evaluate architectural options, and model use cases and ROI for proposed features.
• Monitor and incorporate relevant interconnect standards (PCIe, UCIe, CXL, and emerging die-to-die/optical standards) into architecture decisions.

Requirements

Must-have technical skills and experience for immediate contribution; nice-to-have items listed separately.

• Proven ownership of high-speed SerDes and analog/mixed-signal system architectures (PLLs, TIAs, drivers, equalizers, ADC/DACs, CDRs) for 56G/112G/224G+ PAM4 systems in advanced CMOS (FinFET/GAA).
• System-level architecture experience taking heterogeneous SoCs from concept through architecture sign-off; experience with advanced packaging (2.5D/3D) is expected.
• Expertise in electrical–optical link budget analysis, including transmitter impairments, channel loss, reflection, crosstalk, and receiver noise.
• Hands-on characterization experience with high-speed lab equipment (BERTs, high-speed oscilloscopes, VNAs) and measurement environments.
• Strong understanding of high-speed interconnect standards (PCIe, UCIe, CXL) and their impact on analog/RF architecture.
• Proven collaboration skills across photonics, packaging, digital, product, and customer stakeholders and strong technical communication.
• Experience with architecture and modeling tools: Cadence Virtuoso/Spectre, MATLAB/Simulink, Keysight ADS, HSPICE, Ansys HFSS/SIwave, and Python-based modeling/automation.
• Nice-to-have: silicon photonics or electro-optic interface design, analog design team leadership, system-level SerDes/optical link modeling, and semiconductor product reliability/qualification experience.

Education Requirements

Ph.D. in Electrical Engineering or a related discipline with 5+ years of relevant experience, or a Master’s degree with 8+ years of relevant experience, or equivalent demonstrated impact. Fields referenced include Electrical Engineering or related technical disciplines. No specific certifications were listed.

About the Company

Company: Black Semiconductor

Headquarters: Aachen, Germany

Black Semiconductor is revolutionizing the semiconductor industry with innovative graphene solutions that enhance chip connectivity and efficiency. By merging electronic computing and photonic communication, the company aims to reshape how chips interact, driving significant advancements in power and speed. Their human-centered approach fosters collaboration and continuous learning, making it a dynamic place for professionals to grow and make an impact.