Senior Hardware Engineering Engineer

Role Summary

The Senior Hardware Engineering Engineer will develop advanced embedded memory test and SLM architectures and drive the verification process. You will work in a collaborative environment focusing on chip design and verification.

Experience Level

Mid-level, with 2-4 years of relevant experience in ASIC digital design and verification.

Responsibilities

Key responsibilities include:

• Developing and modeling RTL logic in Verilog for embedded memory test and SLM IP blocks.
• Performing digital design validation and functional verification at both block and SoC levels.
• Executing logic synthesis, static timing analysis, and generating fault coverage reports.
• Applying DFT (Design-for-Test) expertise for comprehensive memory and logic testing.
• Troubleshooting design timing and DFT functional issues.
• Scripting in languages such as Tcl to automate design and verification workflows.
• Maintaining technical collateral including test suites and documentation.

Requirements

Must-have skills include:

• Proficiency in RTL simulation, logic synthesis, and timing verification tools.
• Strong understanding of DFT architectures.
• Familiarity with debug tools such as Verdi.
• Programming skills in SystemVerilog, UVM, Verilog, C/C++, Python, and Tcl.
• Experience with EDA tools such as VCS, Verdi, and DC.

Education Requirements

Not specified.

About the Company

Company: Synopsys

Headquarters: Mountain View, California, USA

Synopsys is a leading company in electronic design automation (EDA) and semiconductor IP solutions. It provides tools and services for designing and verifying complex semiconductor devices and systems. The company plays a pivotal role in the semiconductor industry, helping engineers innovate and deliver higher-quality products faster. Synopsys is committed to advancing technology standards and offers a range of software and hardware solutions to its clients globally.