Senior Front End Design Engineer (Microarchitecture)
CerebrasJob Title
Senior Front End Design Engineer (Microarchitecture)
Role Summary
Senior front-end RTL/microarchitecture engineer responsible for designing and integrating high-performance, power-efficient blocks for the next generations of the Cerebras Wafer Scale Engine (WSE). Works closely with verification, physical design, software and system teams and external vendors to move features from specification to silicon bring-up.
Experience Level
Senior — 8+ years of experience delivering complex, high-performance RTL designs as indicated in the posting.
Responsibilities
Design, integrate, and debug RTL and microarchitecture to meet performance, power, and area goals; collaborate across engineering functions and with external partners during development and silicon bring-up.
- Define functional specifications and micro-architecture for chip blocks.
- Develop, review and deliver RTL suitable for synthesis.
- Drive synthesis and implementation trade-offs to meet PPA targets in coordination with physical design (PD).
- Coordinate with design verification and DFT teams to achieve required functional and test coverage.
- Integrate third-party IP and front-end chip blocks into the system-level design.
- Collaborate with software and system teams to maximize product performance and features.
- Investigate and debug silicon-level functional, timing, and power issues during bring-up.
Requirements
Concise list of must-have technical qualifications followed by useful extras.
- Must-have: Minimum 8+ years delivering complex, high-performance RTL designs.
- Must-have: Front-end chip integration and third-party IP integration experience.
- Must-have: Experience in networking, high-performance computing, machine learning, or closely related domains.
- Must-have: Proven track record of multiple silicon successes and experience collaborating with external vendors.
- Must-have: Knowledge of networking stacks and protocols including TCP/IP, RDMA, and Ethernet.
- Must-have: Familiarity with PCIe, CPU interfaces, and SerDes technologies.
- Must-have: Scripting experience (Python, TCL) for automation and tool integration.
- Logistics: Able to work in a hybrid work environment in Bengaluru, India.
Nice-to-have / assets:
- Experience with FPGA development toolchains and flow (place & route, floorplanning, timing analysis).
- Experience managing external ASIC vendors through the product development cycle.
Education Requirements
Master's degree in Computer Science, Electrical Engineering, or equivalent practical experience (the posting also accepts equivalent experience in lieu of the degree).
About the Company
Company: Cerebras
Headquarters: Sunnyvale, CA, USA
Developer of wafer-scale AI accelerators, Cerebras designs the Wafer Scale Engine (WSE)—one of the world’s largest AI chips—to deliver high-speed training and inference solutions for model labs, enterprises, and AI-native startups.
