Senior FPGA IP Design Engineer

Job Title

Senior FPGA IP Design Engineer

Role Summary

Own the architecture, micro-architecture, and parameterizable RTL design of high-performance soft IP blocks (for example, AMBA AXI interconnect and system interfaces) and ensure portability, scalability, and timing closure across FPGA architectures. Work closely with verification, physical design, field application, and delivery teams to drive designs from specification through deployment.

Experience Level

Senior - typically 5+ years of RTL/FPGA design experience.

Responsibilities

Deliver RTL micro-architectures and production-quality IP while collaborating with cross-functional teams.

• Define micro-architecture and implement RTL for schedulers, command pipelines, coherency/ordering logic, and system interfaces.
• Develop RTL from scratch and provide fixes for regression failures identified during verification.
• Collaborate with verification to shape test plans, improve coverage, and debug regression failures.
• Work with physical design to resolve timing, power, and congestion issues and achieve timing closure.
• Apply CDC and RDC analysis practices within the design flow.
• Provide technical support to FAE/AE teams for pre-sales and post-sales engagements.
• Mentor and provide technical guidance to other engineers while remaining a hands-on contributor.

Requirements

Must-have technical skills and tools; qualifications summarized separately.

• Deep, hands-on knowledge of the AMBA AXI4 protocol suite and high-speed memory interfaces.
• Proficiency with FPGA implementation tool flows and EDA simulation (examples: Siemens Questa/ModelSim, Synopsys VCS).
• Strong scripting skills for build and test automation (Python, Tcl, or Perl).
• Practical experience with CDC (Clock Domain Crossing) and RDC (Reset Domain Crossing) considerations.
• Experience debugging regression failures and delivering RTL fixes.
• Demonstrated ability to collaborate with verification and physical design teams on timing and power closure.
• Good communication skills for technical support to customer-facing teams.

Education Requirements

Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related field. The role expects ~5+ years of dedicated RTL/FPGA design experience.

About the Company

Company: Altera

Headquarters: Bengaluru, Karnataka, India

Altera provides leadership programmable solutions for applications ranging from cloud to edge, unveiling limitless AI possibilities. Their extensive product portfolio includes FPGAs, CPLDs, Intellectual Property, development tools, and System on Modules aimed at accelerating innovation in various fields.