Senior FPGA Engineer (Xilinx) - Video Processing Solution Owner (VHDL)

Job Title

Senior FPGA Engineer (Xilinx) - Video Processing Solution Owner (VHDL)

Role Summary

Lead architect and owner for FPGA-based video processing solutions, responsible for full lifecycle delivery from high-level architecture and RTL development through timing closure, hardware bring-up, and system integration. Work on high-performance, real-time video pipelines and integrate high-speed interfaces in a multidisciplinary engineering environment.

On-site in Seattle with a hybrid schedule (primarily on-site). This role requires hands-on lab validation and close collaboration with firmware, software, and systems engineering teams.

Experience Level

Senior-level - requires 8+ years of FPGA development and system architecture experience.

Responsibilities

Own design, implementation, and delivery of FPGA video-processing hardware and RTL.

• Architect and implement high-performance video processing pipelines (scaling, color-space conversion, frame-rate handling) in RTL.
• Design modular FPGA micro-architectures and integrate internal and third-party IP cores for reuse and performance.
• Develop and maintain custom VHDL and Verilog/SystemVerilog implementations focused on low latency and resource efficiency.
• Define clocking strategies, manage multiple clock domains, and specify timing constraints.
• Perform synthesis, floorplanning, and timing-closure using Xilinx Vivado for high-utilization designs.
• Integrate high-speed interfaces (PCIe, DDR4, 10GbE, HDMI, DisplayPort, MIPI, SDI) and implement AXI-streaming and memory-mapped interfaces.
• Conduct hardware bring-up and system-level debugging using lab instrumentation to validate RTL on silicon.
• Collaborate across teams to translate system requirements into scalable RTL and ensure RTL-to-board connectivity.
• Define and document technical specifications, interface protocols, and timing constraints.

Requirements

Clear must-have technical skills and platform experience; desirable items listed separately.

• Must-have: 8+ years of FPGA development with demonstrated ownership of end-to-end FPGA solutions.
• Must-have: Senior-level experience with Xilinx architectures (UltraScale+, 7-Series) and advanced use of Vivado including floorplanning and timing closure.
• Must-have: Proficient in both VHDL and Verilog/SystemVerilog for custom RTL design (beyond IP integration).
• Must-have: Extensive experience with real-time video/audio pipelines for 4K signals and familiarity with HDMI, DisplayPort, MIPI CSI-2/DSI-2, and SDI standards.
• Must-have: Strong Zynq/SoC experience including PL-to-PS data movement (DMA, interrupts) and integration of hard/soft processors.
• Must-have: Hands-on hardware/software integration and bench debugging experience on new silicon.
• Must-have: Authorization: U.S. Citizens or Permanent Residents only.
• Nice-to-have: Video compression knowledge (H.264/H.265/JPEG-XS), embedded Linux scripting and Vivado/TCL automation, and experience with FPGA CI/CD pipelines (Jenkins, GitLab CI).
• Nice-to-have: Experience implementing audio resampling in RTL and proven cross-disciplinary leadership in multidisciplinary ownership environments.

Education Requirements

Not specified.

About the Company

Company: Riccione Resources

Technical staffing and recruitment firm specializing in placing engineering and technology professionals, particularly in hardware, embedded systems, and FPGA roles. Provides talent solutions to companies seeking experienced engineering staff.