Senior FPGA Engineer

Job Title

Senior FPGA Engineer

Role Summary

Design and deliver production-grade FPGA prototypes for high-performance PCIe applications, owning RTL architecture through timing closure and hardware bring-up. Work on a multidisciplinary engineering team in Porto collaborating with hardware, software, and verification engineers to validate system-level designs prior to silicon.

This role focuses on reliable, high-performance PCIe implementations and supporting compliance testing and hardware validation activities.

Experience Level

Senior - ideally 8+ years of FPGA design and development experience, with a track record of shipping working designs and delivering production-ready prototypes.

Responsibilities

Key day-to-day responsibilities include:

• Prototype and optimize PCIe-based designs on FPGA platforms using Vivado or similar toolchains; drive synthesis, place-and-route, timing closure, and hardware bring-up.
• Simulate and verify PCIe prototypes using industry verification methodologies (e.g., UVM) to ensure correct functionality before hardware implementation.
• Perform timing analysis and multi-clock domain optimization; resolve setup/hold violations and meet performance targets.
• Develop and execute test plans to validate functionality, performance, and reliability of FPGA prototypes in real-world conditions.
• Debug hardware, protocol, and system-level issues uncovered during compliance testing and bring-up; coordinate fixes across prototype and test environments.
• Collaborate with hardware, software, and verification teams to define requirements, evaluate trade-offs, and deliver integrated FPGA solutions.
• Represent the team at industry compliance events (e.g., PCI-SIG workshops) and support official compliance testing activities.

Requirements

Must-have technical skills and experience; nice-to-have items noted.

• Extensive practical FPGA design experience (ideally 8+ years) with shipped designs.
• Deep proficiency in Verilog and RTL design, including complex state machines, pipelines, and multi-clock architectures.
• Strong command of Vivado or equivalent FPGA toolchains, including synthesis, implementation, and timing closure workflows.
• Solid understanding of digital design fundamentals: clock domain crossings, metastability, timing constraints, and static timing analysis.
• Experience with high-speed interfaces such as PCIe or Ethernet, including protocol-level debugging and validation.
• Ability to diagnose hardware vs. simulation discrepancies using systematic debugging methods and to produce clear documentation.
• Nice to have: experience with scripting/automation using Python or Tcl; familiarity with industry verification methodologies (UVM) is a plus.

Education Requirements

Bachelor's or Master's in Electrical Engineering, Computer Engineering, or a related technical field, or equivalent hands-on practical experience.

About the Company

Company: Synopsys

Headquarters: Mountain View, California, USA

Synopsys is a leading company in electronic design automation (EDA) and semiconductor IP solutions. It provides tools and services for designing and verifying complex semiconductor devices and systems. The company plays a pivotal role in the semiconductor industry, helping engineers innovate and deliver higher-quality products faster. Synopsys is committed to advancing technology standards and offers a range of software and hardware solutions to its clients globally.