Senior FPGA Developer: VHDL/Verilog & Verification

Job Title

Senior FPGA Developer: VHDL/Verilog & Verification

Role Summary

Senior FPGA Developer responsible for FPGA/ASIC design, RTL coding, and verification for embedded/firmware projects. Works within an engineering team in Rochester to translate requirements into specifications, implement VHDL/SystemVerilog code, and validate designs through simulation and hardware testing.

Experience Level

Senior — requires approximately 7 years of relevant FPGA/ASIC development and verification experience.

Responsibilities

Primary responsibilities include design, implementation, and verification of FPGA-based systems:

• Analyze requirements and create technical specifications for FPGA/firmware features.
• Develop RTL using VHDL and SystemVerilog.
• Perform functional verification, simulation, and debug of designs.
• Integrate and test firmware on target hardware (board bring-up, lab validation).
• Collaborate with cross-functional teams (firmware, hardware, verification) to resolve issues.
• Use vendor-specific FPGA toolflows for synthesis, implementation, and bitstream generation.
• Document designs, test plans, and verification results.

Requirements

Must-have technical skills and clearances:

• Approximately 7+ years of FPGA/ASIC development and verification experience.
• Proficient in VHDL and SystemVerilog for RTL design and verification.
• Experience with vendor FPGA toolchains (examples: Xilinx Vivado, Intel/Altera toolflows).
• Experience with simulation, synthesis, timing closure, and hardware bring-up.
• Ability to obtain U.S. Secret clearance.

Education Requirements

Requires a Bachelor's degree. (Posting specifies "Bachelor's Degree" but does not list field of study or mention equivalent-experience language.)

About the Company

Company: CodeGeniusRecruit

Recruiting/staffing firm focused on technology and engineering roles, matching candidates with employers for remote, contract, and full-time positions.