Senior Engineer - Verification Enablement, Test Structure Design and Layout

Job Title

Senior Engineer - Verification Enablement, Test Structure Design and Layout

Role Summary

Support development and validation of advanced process technology by enabling verification flows for scribe test-structure design, layout, CAD, and reticle creation within the R&D Scribe Design Group.

Work with cross-functional teams (probe, assembly, test, process integration, product engineering, standards, CAD, and modeling groups) to validate designs and ensure manufacturability.

Experience Level

Senior — typically 5–8 years of relevant experience in IC design flow development, memory and mixed-signal design and layout.

Responsibilities

Primary responsibilities include enabling and validating test-structure and layout flows, supporting tape-outs, and coordinating across teams.

• Design, layout, and optimization of memory/logic/analog circuits and scribe test structures.
• Perform parasitic modeling, post-layout validation, and support reticle experiments and tape-out revisions.
• Manage layout tasks including floor-planning, placement, and routing.
• Execute verification using industry-standard simulators and modeling tools.
• Collaborate with cross-functional teams to ensure accuracy and manufacturability of product designs.
• Drive standardization, solicit guidance from standards/CAD/modeling teams, and improve design quality and verification flows.

Requirements

Must-have technical skills and experience; preferred items listed separately.

• 5–8 years experience in IC design flow development, memory or mixed-signal design and layout.
• Practical experience with SPICE simulators (HSPICE, Finesim) and post-layout verification workflows, including schematic entry and netlist extraction.
• Familiarity with semiconductor electrical fundamentals and device physics.
• Experience automating IC design flows using SKILL, Perl, Python, Bash, or C-Shell.
• Ability to work in multi-functional, multi-site teams across time zones.

Nice-to-have:

• Understanding of physical verification (LVS, DRC, PEX) and rule-deck coding using Calibre SVRF/TVF.
• Knowledge of machine learning algorithms and methodologies.
• Experience maintaining intranet portals (Confluence, SharePoint) and familiarity with Microsoft Power BI.

Education Requirements

Master's degree or higher in Electrical/Electronics Engineering or a related technical field is required.

About the Company

Company: Micron Technology

Headquarters: Boise, Idaho, USA

Micron Technology is a global leader in memory and storage solutions, dedicated to transforming how the world uses information. The company offers a diverse portfolio of high-performance DRAM, NAND, and NOR memory products under the Micron and Crucial brands. With a commitment to customer focus and technological innovation, Micron drives advancements in artificial intelligence, 5G, and other data-centric applications, empowering users to learn, communicate, and progress.