Senior Engineer RTL Design
Arrow ElectronicsJob Title
Senior Engineer, RTL Design
Role Summary
Responsible for RTL development and front-end ASIC/FPGA design within the hardware engineering team. Deliver RTL from specification through netlist, support sustainment work, and collaborate with board-level hardware engineers on system-level design and validation.
Experience Level
Senior — typically requires 5–7 years of related experience; works independently, solves complex problems, and provides informal guidance to junior staff.
Responsibilities
Primary responsibilities include:
- Develop RTL for ASIC and FPGA designs (specification to RTL and netlist).
- Architect modules, perform RTL coding and implement lint and CDC checks.
- Complete front-end design flow tasks from spec to netlist.
- Support and maintain existing/sustenance designs.
- Collaborate with hardware/board design engineers on system- and board-level block diagrams and hardware validation.
- Contribute to process improvements and act as a resource for less-experienced colleagues.
Requirements
Must-have technical skills and experience:
- Proven RTL design and coding experience for ASIC/FPGA projects.
- Practical experience with linting and CDC closure methodologies.
- Familiarity with front-end design flow (specification, RTL, netlist).
- Ability to work independently and support sustainment efforts.
- Experience collaborating with hardware teams on board/system validation.
Education Requirements
Typically a four-year Bachelor's degree is expected; alternatively a Master's degree with reduced experience. The posting accepts equivalent practical work experience in lieu of formal degrees.
About the Company
Company: Arrow Electronics
Headquarters: Centennial, Colorado, United States
Global technology solutions provider and distributor of electronic components, software and services. Serves commercial and industrial markets with design engineering, product realization, supply chain and IoT solutions; parent company of eInfochips.
