Senior Engineer, R2G Methodology and PD Execution

Job Title

Senior Engineer, R2G Methodology and PD Execution

Role Summary

Responsible for executing and optimizing the RTL-to-GDS implementation flow for high-performance CPU cores, owning block-level implementation and delivering PPA (Power, Performance, Area) closure on leading-edge process nodes.

Works within the methodology and core engineering teams to produce production-ready flows, improve automation, and apply ML-enhanced techniques to meet aggressive frequency and power targets.

Experience Level

Senior — requires 4+ years of hands-on experience in Physical Design/Methodology and digital implementation.

Responsibilities

Primary responsibilities include execution, validation, and continuous improvement of RTL-to-GDS flows and ownership of medium-sized CPU sub-block implementations.

• Implement, validate, and maintain production-ready RTL-to-GDS recipes using Synopsys Fusion Compiler and related tools.
• Take end-to-end block ownership from RTL synthesis through final GDS sign-off.
• Drive block-level PPA closure using timing-driven placement, CTS, and routing techniques.
• Apply ML optimization tools for design space exploration to meet PPA targets.
• Identify, debug, and resolve flow and tool-related issues; collaborate with methodology and core teams to remove bottlenecks.
• Coordinate with IP teams (SRAM/standard cell) and technical leads to model and mitigate PPA impacts.
• Develop and maintain robust Tcl/Python automation to improve flow efficiency and repeatability.

Requirements

Must-have technical skills and conditions for the role.

• 4+ years hands-on experience in Physical Design and methodology with a track record in digital implementation.
• Practical experience with FinFET nodes (N5/N3) and related implementation challenges.
• Deep hands-on knowledge of Synopsys digital implementation tools (Fusion Compiler, ICC2, PrimeTime, StarRC).
• Strong understanding of physical design concepts: floorplanning, pin assignment, timing budgeting within hierarchical flows.
• High proficiency in Tcl and Python for flow customization, debugging, and data analysis.
• Demonstrated ability to analyze and resolve complex timing, power, and congestion issues in high-speed, high-density blocks.
• Effective communicator with proven ability to collaborate across structured engineering teams and meet technical milestones.
• Employment contingent on right-to-work verification in India and export-control authorization (background/reference checks and export license as required).

Nice-to-have:

• Familiarity with N2/GAAFET challenges and next-generation process considerations.
• Experience with ML optimization toolchains (e.g., DSO.ai) and hierarchical closure methodologies.

Education Requirements

Not specified.

About the Company

Company: SiFive

Headquarters: San Mateo, California, United States

SiFive is a pioneering company in the RISC-V ecosystem, focused on transforming the future of computing by delivering high-performance, data-intensive RISC-V solutions. Their compute platforms empower leading technology firms to innovate across various markets, including AI, machine learning, and automotive sectors. SiFive is recognized for its commitment to ongoing innovation and fostering collaboration among talented teams, impacting lives by enabling advanced chip design.