Senior Engineer, PLL Design

Job Title

Senior Engineer, PLL Design

Role Summary

Design and develop high-performance PLL and clocking subsystems for RF transceivers, SerDes, and high-speed I/O in advanced deep-submicron CMOS technologies. Work on transistor-level design, system-level modeling, verification, and silicon bring-up while collaborating with digital, layout, and systems teams in San Jose, CA.

This role focuses on technical execution and cross-disciplinary delivery of PLL IPs meeting performance, power, and area targets.

Experience Level

Senior. Experience expectations vary by degree: Bachelor's +5 years, Master's +3 years, PhD 0 years (as stated in the posting).

Responsibilities

Primary responsibilities include:

• Design PLLs and clock-generation circuits (integer-N, fractional-N, digital PLLs, clock multipliers/dividers) for RF and SerDes applications.
• Create and optimize PLL building blocks: VCO/DCO, charge pumps, loop filters, phase/frequency detectors, dividers, and phase interpolators.
• Perform system-level modeling, noise analysis, and jitter budgeting using MATLAB/Simulink.
• Drive design verification: transistor-level simulation, Monte Carlo analysis, and silicon correlation.
• Collaborate with digital, layout, and systems teams to meet performance, power, and area targets for PLL IP.
• Support silicon bring-up, characterization, and lab debug of prototypes.

Requirements

Key technical requirements and skills.

• Extensive hands-on PLL design experience in deep sub-micron CMOS (5nm–28nm) including at least one topology: integer-N, fractional-N, digital PLL, or sub-sampling PLL.
• Strong understanding of PLL system theory: phase noise, jitter, loop dynamics, reference spurs, and fractional spurs.
• Proficiency with IC design CAD tools such as Spectre, SpectreRF, and AMS simulator.
• Strong MATLAB/Simulink skills for behavioral modeling and system-level analysis.
• Familiarity with Verilog/SystemVerilog for mixed-signal simulation and RTL for digital calibration logic.
• Layout-aware design experience and ability to guide critical PLL layout (LC tank, charge pump, reference path).
• Lab characterization experience: phase noise measurement, jitter analysis, and spectrum analysis equipment.
• Experience implementing PLL-related digital calibration (frequency/phase calibration, background self-calibration).
• Excellent problem-solving, analytical, and communication skills.

Nice-to-have:

• Direct experience with SerDes and RF transceiver clocking subsystems.
• Prior silicon bring-up and cross-team IP delivery on advanced nodes.

Education Requirements

Bachelor's degree with 5+ years of experience, Master's degree with 3+ years of experience, or PhD (no minimum experience stated) in Electrical Engineering, Computer Engineering, Computer Science, Physics, Mathematics, or a related technical field. (These degree/experience combinations were specified in the posting.)

About the Company

Company: Samsung Semiconductor

Headquarters: San Diego, California, United States

Samsung Semiconductor is a global leader in semiconductor technology, providing innovative solutions for diverse applications including smartphones, electric vehicles, and data centers. As part of Samsung's Advanced Institute of Technology, the company focuses on cutting-edge research in areas such as CPU microarchitecture, AI, and HPC, fostering a diverse and inclusive work environment for its employees to thrive and innovate.