Senior Engineer, Physical Design (PnR Implementation & Methodology)
SynopsysJob Title
Senior Engineer, Physical Design (PnR Implementation & Methodology)
Role Summary
Responsible for place-and-route (PnR) implementation, flow methodology, signoff support, and PPA optimization for advanced semiconductor designs. Works within a physical-design engineering team and collaborates with cross-functional and geographically distributed engineering groups to improve implementation quality and automation.
Experience Level
Senior-level. The posting specifies degree-based experience guidance: B.Tech/BS holders with 3+ years of relevant experience or M.Tech/MS holders with 2+ years; overall this is an experienced individual contributor role.
Responsibilities
Execute and optimize PnR implementation and flow methodology for complex designs, support signoff, and drive PPA improvements.
- Drive place-and-route (PnR) implementation for complex semiconductor designs.
- Execute and optimize physical-design flows across PnR lifecycle stages.
- Use Fusion Compiler and/or Innovus for design implementation.
- Support physical-design signoff using tools and methodologies such as ICV, RedHawk, PrimeTime, StarRC, or equivalents.
- Analyze implementation results and identify opportunities to improve power, performance, and area (PPA).
- Debug complex implementation and flow issues; contribute to flow robustness and automation.
- Collaborate with cross-functional, multi-geography engineering teams to resolve design and signoff issues.
Requirements
Technical must-haves and preferred skills for successful performance in this role.
- Must-have: Hands-on experience in PnR design implementation and PnR flow methodologies.
- Must-have: Practical experience with Synopsys Fusion Compiler and/or Cadence Innovus.
- Must-have: Solid understanding of PnR development flow and physical-design signoff practices.
- Must-have: Exposure to signoff and analysis tools such as ICV, RedHawk, PrimeTime, StarRC, or equivalent.
- Must-have: Proven ability to analyze results and drive PPA improvements and flow optimizations.
- Must-have: Strong debugging, analytical, and problem-solving skills; effective collaboration in matrixed, cross-cultural teams.
- Nice-to-have: Experience with AI-assisted engineering/productivity tools (for example Cursor) and interest in automation.
Education Requirements
BS/B.Tech in Electrical Engineering (EE), Electronics & Communication Engineering (ECE), or equivalent with 3+ years of relevant experience; OR MS/M.Tech in EE/ECE or equivalent with 2+ years of relevant experience. Equivalent practical experience is acceptable where stated.
About the Company
Company: Synopsys
Headquarters: Mountain View, California, USA
Synopsys is a leading company in electronic design automation (EDA) and semiconductor IP solutions. It provides tools and services for designing and verifying complex semiconductor devices and systems. The company plays a pivotal role in the semiconductor industry, helping engineers innovate and deliver higher-quality products faster. Synopsys is committed to advancing technology standards and offers a range of software and hardware solutions to its clients globally.
