Senior Engineer, Physical Design

Role Summary

The Senior Engineer, Physical Design will work on the physical design and methodology for next-generation high-performance processor chips at Marvell. This role involves collaboration within a global team to ensure efficient design processes targeted at server, 5G/6G, and networking applications.

Experience Level

Mid-level, requiring 3+ years of experience in physical design.

Responsibilities

Key responsibilities include:

• Working on physical design and methodology efficiently for complex chips.
• Triage workflows involving RTL code synthesis and place and route tools.
• Perform timing analyses and ensure a robust power grid through EMIR analysis.
• Review completed runs for errors and optimize successful runs.

Requirements

Must-have skills and experience:

• Bachelor’s, Master’s, or PhD degree in Electrical Engineering, Computer Engineering, or a related field.
• 3+ years of experience in physical design focusing on block-level PNR for advanced CMOS process nodes (7nm, 5nm, or below).
• Experience with EDA tools like Cadence Genus, Innovus, Synopsys Design Compiler, IC Compiler, and Fusion Compiler.
• Knowledge of static timing analysis tools (Tempus or PrimeTime) and analysis tools (Voltus or PrimeRail) is advantageous.
• Familiarity with physical verification and formal verification tools (Calibre, LEC, Formality) is advantageous.
• Willingness to learn and seek new opportunities.

Education Requirements

Bachelor’s, Master’s, or PhD degree in Electrical Engineering, Computer Engineering, or a related field.

About the Company

Company: Marvell Technology

Headquarters: Santa Clara, California, United States

Marvell’s semiconductor solutions serve as essential building blocks of the data infrastructure connecting our world, driving innovation across enterprise, cloud, AI, and carrier architectures. The company focuses on creating transformative technology that shapes the future.