Senior Engineer - Physical Design
SiFiveJob Title
Senior Engineer - Physical Design
Role Summary
As a Senior Physical Design Engineer on SiFive's implementation team, you will lead RTL-to-GDS physical implementation of next-generation IP blocks, focusing on timing closure and power, performance, area (PPA) optimization.
You will collaborate closely with RTL and architecture teams to identify and resolve physical bottlenecks and to drive manufacturable, high-performance layouts across diverse product classes.
Experience Level
Senior - typically 4+ years of hands-on physical design experience on advanced process nodes (7nm and below preferred).
Responsibilities
Primary responsibilities include end-to-end physical implementation and cross-team co-optimization to meet aggressive PPA and reliability targets.
- Own full physical design flow: synthesis, floorplanning, place-and-route, and signoff for major subsystems and IP blocks.
- Collaborate with RTL and architecture teams from early design stages to identify and remove physical bottlenecks (routing congestion, power hotspots, interconnect limits).
- Apply tailored PPA techniques across product classes (low-leakage edge IP, automotive reliability features, high-bandwidth fabrics).
- Debug structural timing violations, routing congestion, and other implementation issues to achieve signoff.
- Improve flows, methodology, and automation; document and promote best practices.
- Mentor and support junior engineers on implementation and signoff processes.
Requirements
Must-have technical skills and experience for this role.
- 4+ years of hands-on physical design experience on advanced process nodes (7nm and below preferred).
- Proven physical implementation experience for at least one major IP domain (CPU, interconnects/fabrics, caches/memory, or accelerators).
- Co-design mindset: ability to analyze how microarchitecture impacts timing, routing, and PPA and propose structural or architectural changes.
- Proficiency with industry EDA implementation and signoff tools - Synopsys (Fusion Compiler, PrimeTime) and/or Cadence (Innovus, Tempus).
- Strong problem-solving skills for complex physical design challenges with minimal supervision.
- Ability to drive technical ownership of implementation tasks and improve design flows and automation.
- Nice-to-have: experience with automotive reliability flows, extreme power optimization techniques, and mentoring junior engineers.
Education Requirements
Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related field.
About the Company
Company: SiFive
Headquarters: San Mateo, California, United States
SiFive is a pioneering company in the RISC-V ecosystem, focused on transforming the future of computing by delivering high-performance, data-intensive RISC-V solutions. Their compute platforms empower leading technology firms to innovate across various markets, including AI, machine learning, and automotive sectors. SiFive is recognized for its commitment to ongoing innovation and fostering collaboration among talented teams, impacting lives by enabling advanced chip design.
