Senior Engineer, Physical Design (ASIC/SoC Place & Route)

Job Title

Senior Engineer, Physical Design (ASIC/SoC Place & Route)

Role Summary

Responsible for end-to-end physical implementation (RTL-to-GDS) including synthesis, floorplanning, placement & routing, clock tree synthesis, STA and signoff for block-level designs and tapeout production chips. Reports to the Manager of Advanced Chip Implementation at the Austin Design Center and works with customers and internal teams to deliver silicon-ready designs.

Role operates on a hybrid schedule with four days in the Austin office.

Experience Level

Senior — requires 7+ years of industry experience.

Responsibilities

Execute and lead physical implementation tasks from netlist to GDS for block- and chip-level designs.

• Complete block-level physical implementation and production tapeout flows.
• Create and evaluate floorplans to meet area, timing, and power targets.
• Design and implement customized clock tree structures and perform place & route.
• Implement ECOs and perform timing closure activities.
• Perform signal integrity (EM/Noise) and power integrity (IR/EM) analysis and fixes.
• Resolve DRC/LVS/ERC/ANTENNA issues and perform physical verification signoff.
• Coordinate with customers and verification/signoff teams to achieve tapeout readiness.

Requirements

Key technical skills and on-site requirements.

Must-have

• Netlist (or RTL)-to-GDS physical implementation experience (place & route, CTS, signoff).
• In-depth knowledge of major EDA tools and physical-design flows.
• Experience with TSMC N16 or more advanced technology nodes.
• Block-level implementation or chip integration and signoff experience.
• Perl and TCL scripting proficiency.
• Ability to work regularly at a customer site in the North Austin, TX area.

Nice-to-have

• Experience with TSMC N5 and more advanced nodes.
• Low-power implementation methodology experience.
• Advanced timing signoff methodologies and STA expertise.
• Proven ability to independently complete Netlist-to-GDS P&R and signoff tasks.
• Track record of multi-million-gate production tapeouts.

Education Requirements

Master's degree in Electrical Engineering or Computer Science is specified. The posting also requires 7+ years of industry experience.

About the Company

Company: TSMC

Headquarters: Hsinchu, Taiwan

TSMC is the world’s leading dedicated semiconductor foundry, offering advanced process technologies, manufacturing capacity and design enablement services to global customers. Founded in 1987, it supports chip production and R&D across Asia, Europe and North America.