Senior Engineer - Low Power CLP
ArmJob Title
Senior Engineer - Low Power CLP
Role Summary
Validate RTL-to-Gate and Gate-to-GDS implementations with a focus on low-power structural verification and logical equivalence checking to enable silicon signoff for SoC and IP designs.
Work within the Solutions Engineering/validation team to develop methodology, influence EDA tool usage, automate flows, and close verification issues across design, verification, and implementation teams.
Experience Level
Senior - 5+ years of relevant experience in logical signoff and low-power verification for SoC/IP projects.
Responsibilities
Key responsibilities include low-power checks, equivalence verification, debugging, and automation to achieve signoff-ready results.
- Perform low-power verification using Cadence Conformal Low Power (CLP) or Synopsys VCLP and validate UPF implementations across RTL, netlist, and physical stages.
- Execute power-aware equivalence checking; analyze and resolve verification failures and non-equivalences.
- Run RTL-to-synthesis, synthesis-to-place-and-route, and ECO logical equivalence checks (LEC) using Cadence Conformal LEC and drive closure.
- Implement SoC-level low-power structural checks and flat LEC signoff runs; produce comprehensive signoff reports.
- Analyze, debug, and resolve CLP/VCLP and LEC aborts and failures through closure with cross-functional teams.
- Develop and maintain automation, TCL/Perl/Python scripts, and reusable verification flows.
- Drive methodology improvements for low-power signoff and verification efficiency.
Requirements
Must-have technical skills and relevant experience; concise list.
- 5+ years of experience in logical signoff and low-power structural verification for complex SoC/IP (must).
- Hands-on experience with UPF/CPF and SystemVerilog (must).
- Practical experience with Cadence Conformal Low Power (CLP) or Synopsys VCLP (must).
- Strong experience with Logic Equivalence Checking (LEC) and power-aware LEC; able to analyze and resolve issues (must).
- Proven ability to debug CLP/VCLP and LEC issues and lead them to closure (must).
- Scripting experience in TCL, Perl, or Python for automation (must).
- Understanding of synthesis and Place & Route (P&R) flows (advantage).
- Experience developing signoff methodology and automation for SoC-level verification (advantage).
Education Requirements
Not specified.
About the Company
Company: Arm
Headquarters: Cambridge, United Kingdom
ARM is a global leader in semiconductor and software design, driving innovation in computing technology. The company specializes in designing processors and systems that provide the essential building blocks for electronic devices. ARM's architecture is widely used in smartphones, servers, and IoT devices, and its collaborative culture fosters bold thinking, diversity, and high-impact benefits for its talented workforce.
