Senior Engineer, Logic Equivalence CAD
Marvell TechnologyJob Title
Senior Engineer, Logic Equivalence CAD
Role Summary
Join the CAD team developing and maintaining logic equivalence checking infrastructure to ensure RTL-to-gate and gate-to-gate functional correctness across Marvell product lines. The role focuses on building robust equivalence flows, debugging mismatches, and integrating with synthesis, DFT, and ECO processes.
Experience Level
Senior level. The posting specifies 2+ years of hands-on experience in equivalence checking and functional ECO flow development.
Responsibilities
Primary responsibilities include developing, deploying, and supporting equivalence flows and related methodologies.
- Develop and maintain RTL2Gate and Gate2Gate equivalence checking flows.
- Debug and root-cause equivalence failures between synthesis/gate representations and RTL.
- Implement functional ECO flows and support ECO-driven fixes.
- Ensure equivalence flows account for pin constraints, don't-verify points, DFT constraints, and power intent.
- Contribute to low-power checks within equivalence methodology.
- Collaborate with synthesis, DFT, and other CAD teams for smooth handoffs and integration.
- Support deployment and ongoing support of flows and interfaces with EDA vendors.
Requirements
Must-have technical skills and experience for immediate contribution.
- Hands-on experience with Cadence Conformal or Synopsys Formality toolsets (experience with both is a plus).
- Strong knowledge of synthesis-to-gate equivalence debug and functional ECO processes.
- Understanding of power intent and multi-power-domain management for equivalence checking.
- Basic RTL coding knowledge and basic DFT concepts (controllability, observability, scan stitching) as they relate to equivalence checks.
- Proficiency in Tcl scripting for flow development.
- Strong analytical and problem-solving skills; effective verbal and written communication; ability to work in a team.
- Nice-to-have: prior experience deploying flows at scale, working directly with EDA vendors, and advanced low-power equivalence techniques.
Education Requirements
Bachelor's or Master's degree in Electrical Engineering or Computer Science. The posting indicates 2+ years of hands-on experience in Equivalence Checking and functional ECO flow development.
About the Company
Company: Marvell Technology
Headquarters: Santa Clara, California, United States
Marvell’s semiconductor solutions serve as essential building blocks of the data infrastructure connecting our world, driving innovation across enterprise, cloud, AI, and carrier architectures. The company focuses on creating transformative technology that shapes the future.
