Senior Engineer II, Verification
MicrochipJob Title
Senior Engineer II, Verification
Role Summary
Senior verification engineer responsible for planning and executing functional verification of digital IP and SoC blocks. The role sits on the verification team and works closely with RTL designers, validation engineers, and system architects to deliver verified silicon.
Primary mission: develop verification environments and testbenches, drive coverage closure, debug design issues, and help achieve sign-off quality for assigned blocks.
Experience Level
Senior level. Specific years-of-experience not specified in the source posting.
Responsibilities
Core responsibilities include designing and executing verification plans and environments, collaborating with cross-functional teams, and ensuring functional correctness.
- Design and implement verification environments and testbenches (SystemVerilog/UVM or equivalent).
- Create directed, constrained-random tests and functional coverage models to validate RTL.
- Plan verification strategy and track coverage closure for IP and SoC blocks.
- Run simulations and debug system and RTL-level failures; triage issues with designers.
- Develop and maintain verification IP, scripts, and automation for simulation and regression flows.
- Work with validation teams during bring-up and silicon debug as needed.
- Mentor junior engineers and contribute to process and methodology improvements.
Requirements
Must-have technical skills and experience expected for the role (based on typical verification responsibilities); specific employer requirements were not provided in the source posting.
- Experience developing verification environments and testbenches using SystemVerilog and UVM (or equivalent).
- Practical knowledge of constrained-random verification, functional coverage, and coverage closure methodologies.
- Experience with simulation tools and regression flows (e.g., VCS, Questa, or equivalents) and debugging RTL-level issues.
- Scripting skills for automation and test development (Python, Perl, Tcl, or similar).
- Strong RTL understanding and ability to read and debug Verilog/VHDL/SystemVerilog code.
- Good communication and cross-team collaboration skills; ability to mentor junior engineers.
Nice-to-have:
- Experience with emulation, FPGA prototyping, formal verification, or low-power verification techniques.
- SoC-level verification experience and familiarity with CI/regression infrastructure.
Education Requirements
Not specified.
About the Company
Company: Microchip
Headquarters: Chandler, Arizona, USA
Microchip is a leading semiconductor company focused on developing innovative solutions to enhance the human experience. With a commitment to empowering innovation, Microchip prioritizes the value of its employees by fostering a culture that supports their growth and contributions.
