Senior Engineer – IC Design (Physical Design - PV/Power/EM/IR Drop Engineer)

Job Title

Senior Engineer – IC Design (Physical Design - PV/Power/EM/IR Drop Engineer)

Role Summary

Join the Silicon Engineering team in Hyderabad as a technical lead focused on physical verification, power integrity, and EM/IR analysis for low-power SoCs. The role requires close collaboration with PD leads, PnR, packaging, and foundry partners and includes mentoring junior engineers.

The primary mission is to ensure signal and power integrity from floorplan through GDSII and tape-out readiness using industry-standard PV and power-analysis methodologies.

Experience Level

Senior-level. The role expects approximately 4+ years of relevant ASIC physical design experience.

Responsibilities

Key responsibilities include:

• Lead and execute end-to-end low-power physical verification flows (DRC, LVS, PERC, resistance checks) from RTL handoff to GDSII.
• Perform static and dynamic IR analysis, EM/IR drop analysis and debugging; define mitigation strategies and fixes.
• Identify grid weaknesses, perform RCA, and implement solutions to meet IR drop targets.
• Collaborate with floorplanning, PnR, IO ring, packaging, and integration teams to resolve physical and power-grid issues.
• Manage GDS streamout, version checks, PG fill insertion, and density/PG checks for sign-off.
• Drive EDA tool automation and methodology improvements for scalability and efficiency.
• Serve as a domain SPOC and mentor junior engineers; coordinate with foundries and vendors for PDK updates and tape-out readiness.

Requirements

Must-have qualifications:

• 4+ years of ASIC physical design experience with emphasis on PV, power, EM and IR-drop analysis.
• Hands-on experience with industry tools such as Cadence Innovus, Cadence Voltus, Synopsys Pegasus, and Mentor Calibre (or equivalent).
• Strong understanding of the architecture-to-GDSII flow and sign-off requirements.
• Proven problem-solving skills, technical leadership, and effective communication.

Nice-to-have:

• Experience in chip-level integration and hierarchical design methodologies.
• Familiarity with place & route and static timing analysis (e.g., IRSTA).
• Knowledge of low-power methodologies (UPF/CPF, power gating, DVFS) and cross-site collaboration experience.

Education Requirements

Bachelor's or Master’s degree in Electronics/Electrical/Computer Engineering (ECE, EEE) or a related technical field.

About the Company

Company: Silicon Labs

Headquarters: Austin, Texas, USA

Silicon Labs is a leading innovator in low-power wireless connectivity, creating embedded technology that connects devices to improve lives. With a focus on advanced edge connectivity applications, the company provides device makers with cutting-edge solutions and support. Headquartered in Austin, Texas, Silicon Labs operates in over 16 countries, serving markets such as smart home, industrial IoT, and smart cities.