Senior Engineer I - Verification

Job Title

Senior Engineer I - Verification

Role Summary

Senior Verification Engineer within the Secure Computing Group responsible for verification of ARM-based SoC blocks, subsystems and chip-level functionality. Work across design, validation and architecture teams to deliver embedded controller solutions.

Primary activities include developing SystemVerilog/UVM test environments, driving coverage closure, debugging RTL and testbench issues, and mentoring junior engineers. Travel: up to 25%.

Experience Level

Senior — typically 4–6 years of ASIC/SoC functional verification experience as stated in the posting.

Responsibilities

Key responsibilities for this role include:

• Own verification for complex blocks and subsystems within ARM-based SoCs.
• Develop block- and chip-level verification test plans and implement directed and constrained-random tests.
• Build SystemVerilog/UVM verification environments and integrate with RTL for simulation and regression runs.
• Generate and analyze functional/code coverage and drive coverage closure.
• Debug RTL and testbench failures; perform root-cause analysis and coordinate fixes with design teams.
• Contribute to automation for regression management, coverage tracking, and debug workflows (including AI/automation initiatives).
• Work with architects and validation engineers to ensure end-to-end feature completeness and quality.
• Provide technical guidance and mentorship to junior engineers; lead cross-site teams as required.

Requirements

Minimum technical and professional requirements.

Must-have:

• Strong expertise in SystemVerilog and UVM verification methodology.
• Hands-on experience developing block/subsystem/SoC-level verification environments and running regressions.
• Knowledge of AMBA, USB, I2C, SPI and eSPI protocols.
• Solid understanding of digital design, RTL fundamentals, and simulation/debug flows.
• Scripting skills for automation (Python, TCL, or Perl).
• Programming skills in C or C++ for test/utility development.
• Proven debugging, problem-solving, and collaboration skills; ability to lead cross-functional teams.

Nice-to-have:

• Experience with Cadence, Synopsys, or Mentor verification platforms and flows.
• Exposure to AI/ML-based verification, emulation, or acceleration.
• Experience with chip-level integration and simulation bring-up.

Education Requirements

Bachelor's or Master's degree in Electrical/Electronic Engineering or a related technical field as stated in the posting.

About the Company

Company: Microchip

Headquarters: Chandler, Arizona, USA

Microchip is a leading semiconductor company focused on developing innovative solutions to enhance the human experience. With a commitment to empowering innovation, Microchip prioritizes the value of its employees by fostering a culture that supports their growth and contributions.