Senior Engineer I - Digital Verification

Job Title

Senior Engineer I - Digital Verification

Role Summary

Member of the Mixed Signal & Linear Business Unit (MSLD) verification team responsible for specifying, building and executing digital verification for high-performance data converters and mixed-signal products that incorporate data converters.

This is a hands-on engineering contributor role focused on verification architecture, environment and methodology development, simulation, debugging, and collaboration with design and validation teams to close verification tasks.

Experience Level

Senior - 5+ years of experience in digital verification (per posting).

Responsibilities

Primary responsibilities include designing verification strategies and executing verification projects for IP and chip levels.

• Define and develop verification architecture, methodologies, and environments.
• Write verification specifications, verification plans, and documentation.
• Develop testbenches, automated regression suites, and test plans.
• Perform block-level and chip-level simulations, verification, and debugging of RTL and logic designs.
• Drive verification to closure using metric-driven methodologies (coverage-driven).
• Collaborate with cross-functional teams and validation for post-silicon debug.
• Mentor junior engineers and present verification plans/results to product teams.

Requirements

Must-have technical skills and experience; preferred items noted separately.

• 5+ years of experience in digital verification (experience requirement).
• Languages: Verilog and SystemVerilog (required).
• Methodology: UVM preferred (OVM/VMM experience acceptable).
• Experience with EDA simulators such as Questasim, VCS, NCSim, or NCVerilog.
• Strong understanding of digital design fundamentals and RTL intent debugging.
• Proficient in Unix and common scripting languages for test automation.
• Expertise in test plan development, functional and code coverage, and assertion-based verification.
• Experience in IP-level verification, constrained-random stimulus, and automated checking.
• Testbench development in Verilog/SystemVerilog following verification methodology.
• Strong simulation and debug skills; familiarity with revision control tools (CVS, GIT).
• Strong written and verbal communication skills; able to work with distributed teams and independently.
• Preferred: mixed-signal verification and real-number modeling.

Education Requirements

Bachelor's or Master's degree in Electronics or equivalent practical experience (the posting explicitly allows equivalent).

About the Company

Company: Microchip

Headquarters: Chandler, Arizona, USA

Microchip is a leading semiconductor company focused on developing innovative solutions to enhance the human experience. With a commitment to empowering innovation, Microchip prioritizes the value of its employees by fostering a culture that supports their growth and contributions.