Senior Engineer I - ASIC Verification

Job Title

Senior Engineer I - ASIC Verification

Role Summary

Responsible for IP-level verification of DDR4/DDR5 memory controllers, PHYs, and AXI interfaces to ensure protocol compliance, data integrity, error handling, and performance for high-speed memory subsystems. Work within a verification team and collaborate with design, firmware, and post-silicon teams to debug RTL and support memory bring-up.

Experience Level

Senior — requires 10+ years of experience in SoC or IP verification, with preference for candidates experienced in memory subsystems.

Responsibilities

Key verification and collaboration duties:

• Develop and maintain SystemVerilog UVM verification environments for DDR4/DDR5 controller and PHY IP.
• Define verification plans, design testbenches, and implement directed and constrained-random testcases.
• Write and debug testcases and sequences covering DDR protocol features (reads/writes, refresh, training, power-down modes).
• Validate ECC, parity, and command/address/data integrity mechanisms; develop scoreboards, assertions (SVA), and checkers.
• Integrate AXI/APB VIPs with DDR subsystems and perform functional and assertion coverage analysis.
• Debug RTL and simulation failures using waveform tools (SimVision, Verdi) and work with design teams on root-cause analysis.
• Collaborate with post-silicon and firmware teams for memory bring-up and validation.
• Mentor junior verification engineers and drive verification best practices and efficiency improvements.

Requirements

Must-have skills and experience; nice-to-have items labeled where appropriate.

• 10+ years of SoC or IP-level verification experience, memory subsystems preferred.
• Strong knowledge of DDR protocols (JEDEC specifications) and memory controller timing parameters.
• Proficient in SystemVerilog and UVM-based verification methodology.
• Hands-on experience with simulators such as Synopsys VCS, Cadence Xcelium, or Mentor Questa.
• Experience with assertions (SVA), scoreboarding, functional and code coverage analysis.
• Experience integrating and verifying AXI protocol interfaces with memory controllers.
• Strong debugging skills using waveform analysis tools and RTL/GLS root-cause analysis.
• Ability to work independently, communicate effectively across teams, and mentor others.
• Comfortable collaborating with firmware and post-silicon teams; travel up to 25%.
• Nice-to-have: familiarity with GLS, Python scripting for automation, and experience applying AI/LLM-assisted workflows to accelerate debug.

Education Requirements

B.E./B.Tech or M.E./M.Tech in Electronics, Electrical, or Computer Engineering.

About the Company

Company: Microchip

Headquarters: Chandler, Arizona, USA

Microchip is a leading semiconductor company focused on developing innovative solutions to enhance the human experience. With a commitment to empowering innovation, Microchip prioritizes the value of its employees by fostering a culture that supports their growth and contributions.