Senior Engineer - HBM Design for Test (DFT)

Job Title

Senior Engineer - HBM Design for Test (DFT)

Role Summary

The Senior Engineer – HBM Design for Test (DFT) will define, implement, integrate, and support DFT solutions across HBM core die and base die for current and next-generation HBM products. The role partners with DFT Architecture, Design Engineering, Product Engineering, Test, and DFT Verification to ensure DFT features meet test, quality, and manufacturability requirements and to support tape-out, silicon bring-up, and qualification.

Experience Level

Senior-level. Typical background: 5+ years in semiconductor development with DFT/design/verification/test or silicon debug experience; plus memory architecture and DFT implementation experience (see Requirements for details).

Responsibilities

Accountable for DFT implementations and coordination across engineering teams to enable testable, manufacturable HBM products.

• Implement and integrate DFT features for assigned HBM core and base die designs per DFT architecture and guidelines.
• Contribute to creation, review, and maintenance of DFT specifications, requirements, and implementation guidelines.
• Ensure DFT implementations support high-quality, efficient, and manufacturable products.
• Collaborate with Design Engineering, Product Engineering, Test, and DFT Verification to translate manufacturing and test requirements into DFT implementations and align verification coverage.
• Identify, debug, and resolve DFT-related issues during build execution, tape-out, and silicon bring-up.
• Serve as a DFT contributor or sub-domain owner for assigned programs or functional areas.
• Support reuse and standardization of DFT logic and methodologies across HBM products under guidance from DFT architecture leadership.
• Participate in design, verification, and readiness reviews; document implementations, lessons learned, and procedures.
• Apply AI tools where appropriate to improve DFT development, verification, or debug processes.

Requirements

Core technical and experience requirements are listed below. Preferred skills and tools follow.

Must-have:

• 5+ years of semiconductor development experience with exposure to DFT, design, verification, test, or silicon debug.
• 1+ years of experience with memory architectures (HBM or DRAM preferred).
• 1+ years implementing DFT features and supporting DFT-related debug and bring-up activities.

Preferred / Nice-to-have:

• Experience working with DFT verification teams and coverage methodologies.
• Familiarity with manufacturing test flows and test requirements for advanced memory products.
• Analog/digital design and verification experience in Cadence environments.
• Strong written and verbal communication skills.

Education Requirements

Bachelor's degree in Electrical Engineering or a related field is required; Master's degree is preferred.

About the Company

Company: Micron Technology

Headquarters: Boise, Idaho, USA

Micron Technology is a global leader in memory and storage solutions, dedicated to transforming how the world uses information. The company offers a diverse portfolio of high-performance DRAM, NAND, and NOR memory products under the Micron and Crucial brands. With a commitment to customer focus and technological innovation, Micron drives advancements in artificial intelligence, 5G, and other data-centric applications, empowering users to learn, communicate, and progress.