Senior Engineer, Digital Design Engineering

Job Title

Senior Engineer, Digital Design Engineering

Role Summary

Senior verification engineer responsible for creating and maintaining SystemVerilog/UVM verification environments, formal property verification (FPV) setups, and firmware-driven tests for SoC blocks. Works with designers and system engineers to verify functionality, protocols, and system-level boot/initialization behavior across simulation, emulation, and post-silicon validation.

Experience Level

Senior - the posting requests at least 3+ years of design verification experience.

Responsibilities

Primary duties include developing verification infrastructure, tests, and proof environments to achieve metric-driven closure and support system-level validation.

• Design and maintain SystemVerilog/UVM verification environments, checkers, scoreboards, assertions, and functional coverage models.
• Develop verification plans and drive closure using code, functional, and assertion coverage plus regression analysis.
• Create constrained-random and directed tests targeting functional, security, and corner-case behaviors.
• Maintain and extend existing testbenches as features evolve.
• Write firmware-driven (C) test cases for embedded processor co-simulation and support firmware integration.
• Architect and implement formal verification environments: FPV wrappers, constraints, clock/reset setup, and proof orchestration.
• Write SystemVerilog Assertions (SVA) for protocol compliance, data integrity, arbitration fairness, and design intent.
• Integrate protocol VIPs and SoC interfaces into verification and formal flows; contribute to top-level SoC verification and emulation activities.
• Collaborate across design, system, and validation teams and assist with post-silicon debug when needed.

Requirements

Must-have technical skills and experience; preferred items listed separately.

• Minimum 3+ years of design verification experience.
• Proficient in SystemVerilog, UVM, and SystemVerilog Assertions (SVA).
• Experienced with functional coverage and constrained-random verification methodologies.
• Hands-on experience building formal property verification environments from scratch (wrappers, constraints, proof strategies).
• Experience writing SVA for bus protocol verification (AMBA AHB/APB/AXI).
• Familiarity with common SoC interfaces: APB, AHB, AXI, QSPI, UART, DMA architectures.
• Experience writing firmware-level tests in C/C++ for verification flows.
• Scripting experience (Python, Tcl, shell).
• Experience with emulation or FPGA prototyping and support for firmware integration and post-silicon validation.
• Willingness to travel up to 10%.

Nice-to-have:

• Experience integrating commercial protocol VIPs (Cadence, Synopsys, or equivalent).
• Familiarity with AI-assisted engineering tools and verification productivity workflows.
• Experience debugging formal counterexamples and refining constraints.
• Familiarity with ARM Cortex-M verification, non-volatile memory verification (ECC, BIST), mixed-signal or analog-on-top verification methodologies, and version control tools (Perforce, Git).

Education Requirements

Bachelor's or Master's degree in Electrical Engineering or Computer Engineering.

About the Company

Company: Analog Devices

Headquarters: Norwood, Massachusetts, USA

Analog Devices is a leading global semiconductor company that bridges the physical and digital worlds, enabling breakthroughs at the Intelligent Edge. With a focus on innovation, ADI develops solutions that drive advancements in digitized factories, mobility, and digital healthcare. The company employs around 24,000 people globally and reported revenues exceeding $9 billion in FY24, creating technologies that transform lives across various sectors.