Senior Engineer, Design Verification (MCU)

Job Title

Senior Engineer, Design Verification (MCU)

Role Summary

Work on end-to-end IP and subsystem verification for MCU-based SoCs, from specification through sign-off. You'll define verification strategies, develop UVM-based environments, drive coverage and closure, and collaborate with RTL, architecture, emulation, and SoC teams.

The role is based in Bengaluru and focuses on verification of MCU peripherals, bus protocols, low-power features and post-silicon debug support.

Experience Level

Senior role. Source specifies 2–4 years of experience in SoC verification domains.

Responsibilities

Primary responsibilities include creating verification plans, building reusable environments, and ensuring IP sign-off with measurable closure.

• Define and execute IP-level verification strategies, test plans, coverage models, and closure criteria.
• Develop scalable, reusable UVM-based verification environments for IP and subsystem verification.
• Drive functional, code, assertion, and cross-coverage closure and report clear metrics.
• Use constraint-random and directed tests to validate protocols, corners, and stress cases.
• Apply AI/ML-assisted verification techniques to accelerate coverage convergence and identify stimulus gaps.
• Collaborate with RTL, Architecture, Emulation, and SoC Verification teams for integration and sign-off readiness.
• Review specifications and translate requirements into verification plans, checkers, and monitors.
• Develop assertions (SVA), scoreboards, and protocol monitors; support Gate-Level Simulation, low-power verification, and post-silicon debug when required.
• Mentor junior engineers and promote verification best practices and continuous improvement.

Requirements

Must-have technical skills and experience for successful performance in this role.

• 2–4 years of experience in SoC verification domains and familiarity with industry-standard EDA toolkits.
• Strong expertise in UVM-based testbench architecture and development.
• Proven experience with metric-driven verification, including functional and code coverage closure.
• Deep knowledge of SystemVerilog, UVM, and assertions (SVA); proficiency in Verilog/SystemVerilog.
• Experience with directed and constrained-random verification methodologies and debugging in simulation, emulation, and post-silicon environments.
• Experience verifying MCU-based SoCs and peripherals (CPU cores, AHB/APB/AXI, interrupt controllers, GPIO, timers, UART, SPI, I2C, CAN, low-power features).
• Working knowledge of C/C++ and shell scripting for testbench automation.
• Strong analytical, problem-solving, and communication skills; ability to work with cross-functional teams and EDA vendors.

Nice-to-have:

• Hands-on experience with AI/ML-based verification tools (coverage gap analysis, stimulus optimization, regression triage).
• Scripting in Python, Perl, or TCL for automation and analytics.
• Exposure to formal verification and hybrid formal-simulation flows.
• Experience with functional safety concepts (ISO 26262), secure boot, low-power verification, or high-speed/complex IPs.
• Firmware development/debugging experience in Embedded C or RTOS-based environments.

Education Requirements

Bachelor's or Master’s degree in Electronics Engineering is required (source specifies these degrees and field).

About the Company

Company: Renesas

Headquarters: Hitachinaka, Japan

Renesas is a global leader in embedded semiconductor solutions, providing high-quality products across automotive, industrial, infrastructure, and IoT sectors. With over 22,000 employees in more than 30 countries, the company focuses on scalable solutions that enhance user experience and drive innovation while committed to sustainability and energy efficiency.