Senior Engineer, Design Verification Engineering

Job Title

Senior Engineer, Design Verification Engineering

Role Summary

Design verification engineer responsible for verification of analog, digital, and mixed-signal ICs. Work with cross-functional design teams to develop models, simulation infrastructure, and self-checking testbenches to validate functionality, accuracy, and performance prior to production.

Role includes establishing metric-driven verification practices, supporting full-chip and mixed-signal verification, scripting for data analysis and automation, and assisting in verification strategy, planning, and debugging to meet delivery timelines.

Experience Level

Senior. The posting specifies experienced-level candidates; company requires a Master's + 2 years or Bachelor's + 4 years of relevant design/verification experience (see Education Requirements for details).

Responsibilities

Core responsibilities include verification planning, testbench and infrastructure development, and cross-team integration and debugging.

• Develop and execute metric-driven verification strategies for analog, digital, and mixed-signal ICs.
• Create SystemVerilog/UVM simulation environments and self-checking testbenches for functionality and performance verification.
• Perform full-chip verification and integrate behavioral models into system-level simulations.
• Build scripts to process simulation data, validate models, and automate test flows.
• Collaborate with analog, digital, and mixed-signal design engineers to produce state-of-the-art models and correlate results across disciplines.
• Debug and resolve design and verification issues; support on-schedule product delivery through planning, resource tracking, and results analysis.
• Promote and adopt verification best practices and coverage-driven methodologies.

Requirements

Must-have technical skills and experience (degree details are summarized separately under Education Requirements).

• Proven expertise in Perl or Python scripting for data processing, automation, and testbench tooling.
• Experience executing full lifecycle of design verification: planning, testbench/test case development, coverage, and system debugging using simulators such as Cadence Xcelium or Synopsys VCS (or equivalent).
• Strong experience with SystemVerilog, UVM, and coverage-driven verification methodologies.
• Practical understanding of analog and digital circuits from prior work or coursework.
• Ability to elicit and communicate complex technical details to stakeholders.

Nice-to-have:

• Experience with behavioral modeling, SPICE/mixed-signal simulation, and full-chip mixed-signal verification.
• Experience driving metric-driven verification programs and developing verification infrastructure at scale.

Education Requirements

Master's degree in Computer Science, Computer Engineering, Electrical Engineering, Electronic Engineering, or a closely related technical field plus two (2) years of experience as a Design Verification Engineer or related IC design/validation role; OR a Bachelor's degree in the same fields plus four (4) years of related experience. Employer will accept foreign education equivalents.

About the Company

Company: Analog Devices

Headquarters: Norwood, Massachusetts, USA

Analog Devices is a leading global semiconductor company that bridges the physical and digital worlds, enabling breakthroughs at the Intelligent Edge. With a focus on innovation, ADI develops solutions that drive advancements in digitized factories, mobility, and digital healthcare. The company employs around 24,000 people globally and reported revenues exceeding $9 billion in FY24, creating technologies that transform lives across various sectors.