Senior Engineer - Design Verification

Job Title

Senior Engineer - Design Verification

Role Summary

Senior individual-contributor in the Interconnect verification team responsible for verifying a next-generation cache-coherent interconnect subsystem used in high-performance SoCs.

Work across architecture, RTL, formal, and verification teams to validate coherent data movement, protocol correctness, ordering, flow control, QoS, and subsystem integration. This role is based in Ahmedabad, India and requires authorization to work in India and may require export-control clearance.

Experience Level

Senior-level. The role expects 5+ years of relevant IP/subsystem/SoC functional verification experience.

Responsibilities

Primary verification responsibilities and expected deliverables:

• Create verification strategies and test plans for assigned interconnect areas.
• Develop and maintain SystemVerilog/UVM verification environments, checkers, scoreboards, assertions, stimulus, and coverage models.
• Verify subsystem behavior across interface boundaries, protocol adaptation layers, and bridge paths (conversion, buffering, deinterleaving, data movement).
• Define and run directed and constrained-random tests to exercise coherency, ordering, backpressure, arbitration, QoS, and integration corner cases.
• Analyze failures, isolate root cause, and drive fixes across RTL, assertions, testbench infrastructure, and test content.
• Write and analyze functional coverage and close coverage holes to achieve verification completeness and signoff quality.
• Collaborate with architecture, design, formal, and software teams to clarify requirements and improve verification early in the cycle.
• Contribute reusable methodology, automation, and debug improvements to raise team productivity and verification quality.

Requirements

Must-have skills and experience; preferred items listed separately.

• Must-have: 5+ years of functional verification experience in IP, subsystem, or SoC verification focused on memory systems, cache, or interconnects.
• Must-have: Hands-on SystemVerilog and UVM verification experience, including testbench development, assertions, checkers, and coverage.
• Must-have: Solid understanding of cache-coherent systems, on-chip interconnects, ordering and flow-control semantics, and related verification techniques.
• Must-have: Proven ability to create test plans, build testbenches, analyze coverage, and debug complex design and protocol issues.
• Must-have: Strong debugging and root-cause skills across specification, RTL, and verification environments; effective cross-team communication.

• Nice-to-have: Direct experience with coherent interconnects, NoC, multicore SoCs, or cache/memory-subsystem verification.
• Nice-to-have: Familiarity with industry protocols such as AXI, CHI, ACE, CXL, UCIe or similar.
• Nice-to-have: Scripting/automation experience (Python or similar), formal verification, performance-oriented verification, or emulation/FPGAs for debug.
• Nice-to-have: History of contributing reusable infrastructure or methodology improvements for verification teams.

Education Requirements

Bachelor's or Master’s degree in Electrical Engineering, Computer Engineering, Computer Science, or a related technical field.

About the Company

Company: SiFive

Headquarters: San Mateo, California, United States

SiFive is a pioneering company in the RISC-V ecosystem, focused on transforming the future of computing by delivering high-performance, data-intensive RISC-V solutions. Their compute platforms empower leading technology firms to innovate across various markets, including AI, machine learning, and automotive sectors. SiFive is recognized for its commitment to ongoing innovation and fostering collaboration among talented teams, impacting lives by enabling advanced chip design.