Senior Engineer - DEG Layout

Job Title

Senior Engineer - DEG Layout

Role Summary

The Senior Engineer is responsible for layout design and delivery of analog, mixed-signal and custom digital blocks, standard cells and chip-level layouts in advanced CMOS processes. The role includes layout development, physical verification, automation, and coordination with global engineering teams to meet project schedules and quality targets.

Experience Level

Senior-level; typically 5–8 years of experience in analog/custom layout design in advanced CMOS processes.

Responsibilities

Key responsibilities include block-level layout delivery, verification, mentoring, and project coordination.

• Design and develop layouts for critical analog, mixed-signal, custom digital blocks, standard cells and full-chip level.
• Perform physical verification: LVS, DRC, antenna checks, shielding, matching, latch-up, electro-migration, IR/EM and related quality checks.
• Develop digital block layouts using auto placement and routing tools where applicable.
• Implement scripting and basic automation (Skill) to improve throughput and quality.
• Use AI and automation tools to reduce layout effort and improve productivity.
• Plan and estimate area/time, schedule work across multiple projects, and ensure on-time delivery.
• Guide and review work of junior engineers and contribute to project-management activities.
• Communicate effectively with global engineering teams to assure project success.

Requirements

Core technical skills and experience required; a few items that add advantage are listed separately.

• Must-have: 5–8 years of hands-on experience in analog/custom layout design in advanced CMOS processes.
• Must-have: Expertise with Cadence VLE/VXL and Mentor Graphics Calibre (DRC/LVS).
• Must-have: Proven experience creating layouts for critical analog blocks (examples: temperature sensors, PLL, ADC, DAC, LDO, bandgap, reference generators, charge pumps, current mirrors, comparators, differential amplifiers).
• Must-have: Strong understanding of analog layout fundamentals (matching, electro-migration, latch-up, coupling/crosstalk, IR-drop, parasitics) and how layout affects speed, capacitance, power and area.
• Must-have: Strong physical verification and problem-solving skills.
• Must-have: Effective verbal and written communication skills.
• Nice-to-have: Multiple tape-out support experience, experience with auto placement & routing tools, scripting/automation experience, and familiarity with AI-driven layout productivity tools.

Education Requirements

Not specified.

About the Company

Company: Micron Technology

Headquarters: Boise, Idaho, USA

Micron Technology is a global leader in memory and storage solutions, dedicated to transforming how the world uses information. The company offers a diverse portfolio of high-performance DRAM, NAND, and NOR memory products under the Micron and Crucial brands. With a commitment to customer focus and technological innovation, Micron drives advancements in artificial intelligence, 5G, and other data-centric applications, empowering users to learn, communicate, and progress.