Senior Engineer - CPU Verification (ALU, FPU Formal and Datapath Verification)
SiFiveJob Title
Senior Engineer - CPU Verification (ALU, FPU Formal and Datapath Verification)
Role Summary
Lead verification planning and execution for ALU and floating-point blocks with emphasis on formal and datapath verification. Collaborate with architecture, design, and verification teams to define verification strategy and improve verification completeness for high-performance CPU cores.
Contribute reusable methodology and automation to raise verification quality and productivity across CPU core programs.
Experience Level
Senior - the posting requests 4+ years of relevant ASIC, CPU/core, or SoC design verification experience.
Responsibilities
Primary responsibilities include verification strategy, environment development, and cross-team collaboration to uncover corner-case bugs and achieve coverage closure.
- Own verification planning and execution for ALU and FPU blocks with focus on formal and datapath verification.
- Define verification approaches for arithmetic, floating-point, operand dependency, bypass/forwarding, replay, flush/recovery, exceptions, and execution-to-commit interactions.
- Drive verification strategy, test planning, debug, coverage analysis, and closure for complex vector, ALU, and FPU execution-pipeline and datapath behaviors.
- Develop assertions, checkers, scoreboards, stimulus, and coverage models that expose corner cases and improve bug-finding efficiency.
- Partner with architecture, design, and verification teams to review specifications, identify risks early, and improve verification completeness.
- Perform root-cause debug across specification, RTL, tests, and verification infrastructure.
- Contribute reusable methodology, automation, and infrastructure to improve verification quality across future CPU core projects.
Requirements
Must-have technical skills and experience for successful performance in this role.
- 4+ years of experience in ASIC, CPU/core, or SoC design verification.
- Hands-on experience with SystemVerilog-based verification and modern verification methodologies.
- Strong understanding of computer architecture and CPU microarchitecture.
- Experience verifying ALU pipelines, floating-point execution, datapath verification, formal verification, issue/dispatch behavior, dependency handling, forwarding, replay, or exception handling.
- Knowledge of verification flow: test planning, stimulus generation, debug, coverage analysis, and coverage closure.
- Programming or scripting skills in Python, C/C++, or similar for DV infrastructure and automation.
- Effective collaboration and debugging skills across architecture, design, performance, and verification teams.
- Ability to pass background checks, provide proof of right to work in India, and meet export-control authorization requirements.
Education Requirements
Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field preferred (as specified in the posting).
About the Company
Company: SiFive
Headquarters: San Mateo, California, United States
SiFive is a pioneering company in the RISC-V ecosystem, focused on transforming the future of computing by delivering high-performance, data-intensive RISC-V solutions. Their compute platforms empower leading technology firms to innovate across various markets, including AI, machine learning, and automotive sectors. SiFive is recognized for its commitment to ongoing innovation and fostering collaboration among talented teams, impacting lives by enabling advanced chip design.
