Senior Engineer, CAD Layout

Job Title

Senior Engineer, CAD Layout

Role Summary

Work as a CAD Engineer on physical layout and verification flows for CMOS memory designs. The role supports production layout teams by evaluating and improving in-house and commercial EDA tools, developing automated workflows, and increasing layout productivity.

Experience Level

Senior-level. The posting requests 5+ years of relevant experience in layout automation, physical verification, or related domains.

Responsibilities

Provide production support, develop automation and methodology, and collaborate with layout teams and global stakeholders.

• Collaborate with memory layout teams to resolve daily production issues and deliver sustainable solutions.
• Identify process bottlenecks and implement improvements to increase layout productivity and time-to-market.
• Implement and lead layout flows using AI-assisted and automated workflows, including copilot-style assistants and rule-aware automation for placement, routing, and optimization.
• Evaluate and deploy new EDA tools and technologies for layout development.
• Develop AI-enabled methodologies for semi-automated floorplanning and parasitic estimation.
• Provide technical guidance and mentorship to junior engineers.

Requirements

Core technical skills and experience required for effective performance in this role.

• Must-have: 5+ years experience in layout automation, physical verification, or related domains.
• Must-have: Experience customizing design environments and developing automation to improve memory layout productivity.
• Must-have: Hands-on experience with place-and-route flows for custom memory layouts and industry tools such as Cadence Virtuoso, Synopsys Custom Compiler, Pulsic Unity, Itools.
• Must-have: Strong programming fundamentals and experience with scripting languages such as Skill (Cadence), Perl, Python, and Tcl; working knowledge of Linux.
• Must-have: Proven ability to work effectively with global teams and stakeholders; strong problem-solving and attention to detail.
• Must-have: Proven expertise in defining, developing, and scaling AI-driven automation and AI-assisted methodologies for complex layout workflows.
• Nice-to-have: Experience with PDN analysis tools (Totem, VoltusXFA/XA) and familiarity with physical verification flows and debugging DRC, LVS, DFM, Antenna/ICV issues.
• Nice-to-have: Knowledge of EMIR, RC extraction, ESD, and latch-up considerations in advanced CMOS processes.

Education Requirements

Bachelor's or Master's degree in Electronics, Electrical, or Computer Engineering.

About the Company

Company: Micron Technology

Headquarters: Boise, Idaho, USA

Micron Technology is a global leader in memory and storage solutions, dedicated to transforming how the world uses information. The company offers a diverse portfolio of high-performance DRAM, NAND, and NOR memory products under the Micron and Crucial brands. With a commitment to customer focus and technological innovation, Micron drives advancements in artificial intelligence, 5G, and other data-centric applications, empowering users to learn, communicate, and progress.