Senior Engineer – Backend (Physical Design & Timing)

Job Title

Senior Engineer – Backend (Physical Design & Timing)

Role Summary

Lead timing closure and sign-off for complex IP and SoC blocks that integrate full-custom ComputeRAM® macros. Drive Static Timing Analysis (STA) across corners and modes, define and maintain clean constraints, and coordinate with synthesis, place-and-route, clock-tree, and full-custom teams to achieve predictable sign-off on modern process nodes.

Experience Level

Senior — typically 5+ years in ASIC physical design with a timing-closure focus (the posting specifies 5+ years).

Responsibilities

Work on timing closure, STA flows, and cross-team integration to produce sign-off-quality results.

• Build, refine, and maintain timing constraints for blocks and top-level designs, including clocks, generated clocks, I/O timing, and exceptions.
• Run STA across corners and modes; close setup and hold and manage variation and correlation from synthesis through P&R to sign-off.
• Define and debug clock-tree strategy; set targets for skew, jitter, and latency; collaborate with P&R on placement, buffering, and routing decisions affecting timing.
• Lead timing and functional ECOs, track impacts, and drive repeatable closure with minimal overhead.
• Support gate-level verification with timing data; ensure timing and constraints match sign-off views.
• Automate timing checks, report generation, and regressions via scripting; create reusable checklists and documentation.

Requirements

Must-have skills and experience required to perform the role.

• 5+ years in ASIC physical design with a strong emphasis on timing closure and sign-off.
• Practical experience with STA tools and flows, including multi-clock and cross-domain designs and hierarchical closure.
• Hands-on collaboration with synthesis and place-and-route to drive timing-aware design choices and ECOs.
• Scripting skills to automate timing analysis, checks, and reporting.
• Proven collaborative approach across front-end, backend, and verification teams.

Nice-to-have:

• Experience with power-aware and low-power backend techniques.
• Background in scan/test timing and interaction with verification and physical verification flows.
• Exposure to advanced nodes and hierarchical sign-off on large designs.
• Experience with accelerators or memory-adjacent designs where timing integration is critical.

Education Requirements

Not specified.

About the Company

Company: Synthara

Headquarters: Zürich, Switzerland

Synthara develops ComputeRAM® hardware and software for efficient on-device AI, providing compilers, drivers, SDKs and tooling to enable AI workloads from microcontrollers to accelerators, with a focus on hardware/software co-design and developer usability.